finished types. wrote top-entity
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@ -1,19 +1,29 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- "work" denotes the curent library. Similar to this in C++, C# etc...
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use work.axi3intercon_pkg.all;
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entity axi3intercon is
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port (
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aclk : in std_logic;
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aresetn : in std_logic
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generic(
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constant MASTER_COUNT : natural := 1;
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constant SLAVE_COUNT : natural := 1
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);
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port(
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aclk : in std_logic;
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aresetn : in std_logic;
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masters_in : out axi_masters_in(0 to MASTER_COUNT - 1);
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masters_out : in axi_masters_out(0 to MASTER_COUNT - 1);
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slaves_in : out axi_masters_in(0 to SLAVE_COUNT - 1);
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slaves_out : in axi_masters_out(0 to SLAVE_COUNT - 1)
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);
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end entity axi3intercon;
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architecture RTL of axi3intercon is
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signal rst : std_logic;
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begin
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reset_sync : process(aclk, aresetn) is
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reset_sync : process(aclk, aresetn) is
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begin
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if aresetn = '0' then
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rst <= '1';
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@ -21,7 +31,5 @@ begin
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rst <= '0';
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end if;
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end process reset_sync;
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end architecture RTL;
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@ -3,17 +3,42 @@ use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package axi3intercon_pkg is
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constant RID_MASTER_BITS : natural := 8;
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constant RID_SLAVE_BITS : natural := 10;
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constant WID_MASTER_BITS : natural := 8;
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constant WID_SLAVE_BITS : natural := 10;
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-- Slave bits have to be more. SLAVE_BITS = MASTER_BITS + log_2(MASTER_COUNT)
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-- Master ID is padded onto ID to identify the transfer internally in the crossbar
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-- This is defined in AXI-3 and -4 Standard.
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constant RID_MASTER_BITS : natural := 12;
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constant RID_SLAVE_BITS : natural := 14;
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constant WID_MASTER_BITS : natural := 12;
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constant WID_SLAVE_BITS : natural := 14;
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constant DATA_BITS : natural := 32;
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constant DATA_STROBES : natural := (DATA_BITS / 8);
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constant ADDRESS_BITS : natural := 32;
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constant MASTER_COUNT : natural := 2;
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constant SLAVE_COUNT : natural := 2;
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constant USER_BITS : natural := 4;
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-- Constant definitions for signals
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--Definitions for burst size
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constant AXI_SIZE_1 : std_logic_vector(2 downto 0) := (others => '0');
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constant AXI_SIZE_2 : std_logic_vector(2 downto 0) := "001";
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constant AXI_SIZE_4 : std_logic_vector(2 downto 0) := "010";
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constant AXI_SIZE_8 : std_logic_vector(2 downto 0) := "011";
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constant AXI_SIZE_16 : std_logic_vector(2 downto 0) := "100";
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constant AXI_SIZE_32 : std_logic_vector(2 downto 0) := "101";
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constant AXI_SIZE_64 : std_logic_vector(2 downto 0) := "110";
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constant AXI_SIZE_128 : std_logic_vector(2 downto 0) := "111";
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-- Definitions for response vector
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constant AXI_RESP_OKAY : std_logic_vector(1 downto 0) := "00";
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constant AXI_RESP_EXOKAY : std_logic_vector(1 downto 0) := "01";
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constant AXI_RESP_SLVERR : std_logic_vector(1 downto 0) := "10";
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constant AXI_RESP_DECERR : std_logic_vector(1 downto 0) := "11";
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-- Definitions for lock locked transactions (only AXI 3 supports locked access mode)
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constant AXI_LOCK_NORMAL : std_logic_vector(1 downto 0) := "00";
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constant AXI_RESP_EXCLUSIVE : std_logic_vector(1 downto 0) := "01";
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constant AXI_RESP_LOCKED : std_logic_vector(1 downto 0) := "10";
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-- type declarations for AW channel
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type master_aw_out is record
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@ -83,7 +108,7 @@ package axi3intercon_pkg is
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wdata : std_logic_vector(DATA_BITS - 1 downto 0);
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wstrb : std_logic_vector(DATA_STROBES - 1 downto 0);
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wlast : std_logic;
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wuser : std_logic; -- user defined
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wuser : std_logic_vector(USER_BITS - 1 downto 0); -- user defined
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wvalid : std_logic;
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end record master_w_out;
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@ -92,7 +117,7 @@ package axi3intercon_pkg is
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wdata : std_logic_vector(DATA_BITS - 1 downto 0);
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wstrb : std_logic_vector(DATA_STROBES - 1 downto 0);
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wlast : std_logic;
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wuser : std_logic; -- user defined
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wuser : std_logic_vector(USER_BITS - 1 downto 0); -- user defined
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wvalid : std_logic;
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end record slave_w_in;
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@ -101,6 +126,94 @@ package axi3intercon_pkg is
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end record master_w_in;
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subtype slave_w_out is master_w_in;
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-- Type declarations for R channel
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type master_r_in is record
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rid : std_logic_vector(RID_MASTER_BITS - 1 downto 0);
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rdata : std_logic_vector(DATA_BITS - 1 downto 0);
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rresp : std_logic_vector(1 downto 0);
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rlast : std_logic;
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ruser : std_logic_vector(USER_BITS - 1 downto 0);
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rvalid : std_logic;
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end record master_r_in;
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type slave_r_out is record
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rid : std_logic_vector(RID_SLAVE_BITS - 1 downto 0);
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rdata : std_logic_vector(DATA_BITS - 1 downto 0);
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rresp : std_logic_vector(1 downto 0);
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rlast : std_logic;
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ruser : std_logic_vector(USER_BITS - 1 downto 0);
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rvalid : std_logic;
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end record slave_r_out;
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type master_r_out is record
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rready : std_logic;
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end record master_r_out;
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subtype slave_r_in is master_r_out;
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-- Type declarations for B channel
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type master_b_in is record
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bid : std_logic_vector(WID_MASTER_BITS - 1 downto 0);
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bresp : std_logic_vector(1 downto 0);
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buser : std_logic_vector(USER_BITS - 1 downto 0);
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bvalid : std_logic;
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end record master_b_in;
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type slave_b_out is record
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bid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0);
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bresp : std_logic_vector(1 downto 0);
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buser : std_logic_vector(USER_BITS - 1 downto 0);
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bvalid : std_logic;
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end record slave_b_out;
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type master_b_out is record
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bready : std_logic;
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end record master_b_out;
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subtype slave_b_in is master_b_out;
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-- Combined definitions
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type axi_master_in is record
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aw : master_aw_in;
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ar : master_ar_in;
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w : master_w_in;
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r : master_r_in;
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b : master_b_in;
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end record axi_master_in;
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type axi_master_out is record
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aw : master_aw_out;
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ar : master_ar_out;
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w : master_w_out;
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r : master_r_out;
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b : master_b_out;
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end record axi_master_out;
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type axi_slave_in is record
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aw : slave_aw_in;
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ar : slave_ar_in;
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w : slave_w_in;
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r : slave_r_in;
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b : slave_b_in;
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end record axi_slave_in;
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type axi_slave_out is record
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aw : slave_aw_out;
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ar : slave_ar_out;
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w : slave_w_out;
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r : slave_r_out;
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b : slave_b_out;
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end record axi_slave_out;
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-- Array definitions
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type axi_masters_in is array (natural range <>) of axi_master_in;
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type axi_masters_out is array (natural range <>) of axi_master_out;
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type axi_slaves_in is array (natural range <>) of axi_slave_in;
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type axi_slaves_out is array (natural range <>) of axi_slave_out;
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end package axi3intercon_pkg;
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-- package body axi3intercon_pkg is
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