modified types to *_t, aw router created and connected
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23
src/axi3-interconnect-aw-router.vhd
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23
src/axi3-interconnect-aw-router.vhd
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@ -0,0 +1,23 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.axi3intercon_pkg.all;
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use work.axi_aw_router_pkg.all;
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entity axi3intecon_aw_router is
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port(
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aclk : in std_logic;
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rst : in std_logic;
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masters_out : in axi_aw_masters_out_t(0 to MASTER_COUNT - 1);
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masters_in : out axi_aw_masters_in_t(0 to MASTER_COUNT - 1);
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slaves_out : in axi_aw_slaves_out_t(0 to SLAVE_COUNT - 1);
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slaves_in : out axi_aw_slaves_in_t(0 to SLAVE_COUNT - 1);
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write_locks : out write_locks_t(0 to MASTER_COUNT - 1);
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write_releases : in write_release_t
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);
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end entity axi3intecon_aw_router;
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architecture RTL of axi3intecon_aw_router is
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begin
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end architecture RTL;
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23
src/axi3-interconnect-aw-router_pkg.vhd
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src/axi3-interconnect-aw-router_pkg.vhd
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@ -0,0 +1,23 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.axi3intercon_pkg.all;
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package axi_aw_router_pkg is
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type axi_aw_masters_in_t is array (natural range <>) of master_aw_in_t;
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type axi_aw_masters_out_t is array (natural range <>) of master_aw_out_t;
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type axi_aw_slaves_out_t is array (natural range <>) of slave_aw_out_t;
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type axi_aw_slaves_in_t is array (natural range <>) of slave_aw_in_t;
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type write_lock_t is record
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locked : std_logic;
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slave_idx : integer range 0 to SLAVE_COUNT - 1;
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end record write_lock_t;
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type write_locks_t is array (natural range <>) of write_lock_t;
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subtype write_release_t is std_logic_vector(0 to MASTER_COUNT -1);
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end package axi_aw_router_pkg;
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-- package body filename is
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-- end package body filename;
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@ -1,27 +1,29 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- "work" denotes the curent library. Similar to this in C++, C# etc...
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use work.axi3intercon_pkg.all;
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use work.axi_aw_router_pkg.all;
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entity axi3intercon is
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generic(
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constant MASTER_COUNT : natural := 1;
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constant SLAVE_COUNT : natural := 1
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);
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port(
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aclk : in std_logic;
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aresetn : in std_logic;
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masters_in : out axi_masters_in(0 to MASTER_COUNT - 1);
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masters_out : in axi_masters_out(0 to MASTER_COUNT - 1);
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slaves_in : out axi_masters_in(0 to SLAVE_COUNT - 1);
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slaves_out : in axi_masters_out(0 to SLAVE_COUNT - 1)
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masters_in : out axi_masters_in_t(0 to MASTER_COUNT - 1);
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masters_out : in axi_masters_out_t(0 to MASTER_COUNT - 1);
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slaves_in : out axi_slaves_in_t(0 to SLAVE_COUNT - 1);
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slaves_out : in axi_slaves_out_t(0 to SLAVE_COUNT - 1)
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);
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end entity axi3intercon;
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architecture RTL of axi3intercon is
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signal rst : std_logic;
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signal write_locks : write_locks_t(0 to MASTER_COUNT - 1);
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signal write_releases : write_release_t;
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signal aw_masters_out : axi_aw_masters_out_t(0 to MASTER_COUNT - 1);
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signal aw_masters_in : axi_aw_masters_in_t(0 to MASTER_COUNT - 1);
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signal aw_slaves_out : axi_aw_slaves_out_t(0 to SLAVE_COUNT - 1);
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signal aw_slaves_in : axi_aw_slaves_in_t(0 to SLAVE_COUNT - 1);
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begin
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reset_sync : process(aclk, aresetn) is
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begin
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@ -32,4 +34,30 @@ begin
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end if;
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end process reset_sync;
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axi3intecon_aw_router_inst : entity work.axi3intecon_aw_router
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port map(
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aclk => aclk,
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rst => rst,
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masters_out => aw_masters_out,
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masters_in => aw_masters_in,
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slaves_out => aw_slaves_out,
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slaves_in => aw_slaves_in,
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write_locks => write_locks,
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write_releases => write_releases
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);
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aw_master_connect : for i in 0 to MASTER_COUNT-1 generate
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aw_masters_out(i) <= masters_out(i).aw;
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masters_in(i).aw <= aw_masters_in(i);
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end generate aw_master_connect;
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aw_slave_connect : for i in 0 to SLAVE_COUNT-1 generate
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aw_slaves_out(i) <= slaves_out(i).aw;
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slaves_in(i).aw <= aw_slaves_in(i);
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end generate aw_slave_connect;
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end architecture RTL;
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@ -17,6 +17,9 @@ package axi3intercon_pkg is
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constant USER_BITS : natural := 4;
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constant MASTER_COUNT : natural := 2;
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constant SLAVE_COUNT : natural := 2;
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-- Constant definitions for signals
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--Definitions for burst size
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@ -41,7 +44,7 @@ package axi3intercon_pkg is
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constant AXI_RESP_LOCKED : std_logic_vector(1 downto 0) := "10";
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-- type declarations for AW channel
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type master_aw_out is record
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type master_aw_out_t is record
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awid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); -- Write transaction ID
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awaddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write address
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awlen : std_logic_vector(7 downto 0); -- Burst length - 1;
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@ -51,13 +54,13 @@ package axi3intercon_pkg is
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awcache : std_logic_vector(3 downto 0); -- caching info
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awprot : std_logic_vector(2 downto 0); -- protection info
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awvalid : std_logic; -- Data valid
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end record master_aw_out;
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end record master_aw_out_t;
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type master_aw_in is record
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type master_aw_in_t is record
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awready : std_logic;
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end record master_aw_in;
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end record master_aw_in_t;
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type slave_aw_in is record
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type slave_aw_in_t is record
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awid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); -- Write transaction ID
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awaddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write address
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awlen : std_logic_vector(7 downto 0); -- Burst length - 1;
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@ -67,12 +70,12 @@ package axi3intercon_pkg is
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awcache : std_logic_vector(3 downto 0); -- caching info
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awprot : std_logic_vector(2 downto 0); -- protection info
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awvalid : std_logic; -- Data valid
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end record slave_aw_in;
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end record slave_aw_in_t;
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subtype slave_aw_out is master_aw_in;
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subtype slave_aw_out_t is master_aw_in_t;
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-- type decalatations for AR cahnnel
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type master_ar_out is record
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type master_ar_out_t is record
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arid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); -- Write transaction ID
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araddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write start address
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arlen : std_logic_vector(7 downto 0); -- Burst length - 1;
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@ -82,13 +85,13 @@ package axi3intercon_pkg is
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arcache : std_logic_vector(3 downto 0); -- caching info
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arprot : std_logic_vector(2 downto 0); -- protection info
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arvalid : std_logic; -- Data valid
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end record master_ar_out;
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end record master_ar_out_t;
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type master_ar_in is record
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type master_ar_in_t is record
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awready : std_logic;
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end record master_ar_in;
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end record master_ar_in_t;
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type slave_ar_in is record
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type slave_ar_in_t is record
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arid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); -- Read transaction ID
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araddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Read start address
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arlen : std_logic_vector(7 downto 0); -- Burst length - 1;
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@ -98,121 +101,121 @@ package axi3intercon_pkg is
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arcache : std_logic_vector(3 downto 0); -- caching info
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arprot : std_logic_vector(2 downto 0); -- protection info
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arvalid : std_logic; -- Data valid
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end record slave_ar_in;
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end record slave_ar_in_t;
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subtype slave_ar_out is master_ar_in;
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subtype slave_ar_out is master_ar_in_t;
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-- type decalarations for W channel
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type master_w_out is record
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type master_w_out_t is record
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wid : std_logic_vector(WID_MASTER_BITS - 1 downto 0);
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wdata : std_logic_vector(DATA_BITS - 1 downto 0);
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wstrb : std_logic_vector(DATA_STROBES - 1 downto 0);
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wlast : std_logic;
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wuser : std_logic_vector(USER_BITS - 1 downto 0); -- user defined
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wvalid : std_logic;
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end record master_w_out;
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end record master_w_out_t;
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type slave_w_in is record
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type slave_w_in_t is record
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wid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0);
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wdata : std_logic_vector(DATA_BITS - 1 downto 0);
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wstrb : std_logic_vector(DATA_STROBES - 1 downto 0);
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wlast : std_logic;
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wuser : std_logic_vector(USER_BITS - 1 downto 0); -- user defined
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wvalid : std_logic;
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end record slave_w_in;
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end record slave_w_in_t;
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type master_w_in is record
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type master_w_in_t is record
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wready : std_logic;
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end record master_w_in;
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end record master_w_in_t;
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subtype slave_w_out is master_w_in;
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subtype slave_w_out is master_w_in_t;
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-- Type declarations for R channel
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type master_r_in is record
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type master_r_in_t is record
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rid : std_logic_vector(RID_MASTER_BITS - 1 downto 0);
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rdata : std_logic_vector(DATA_BITS - 1 downto 0);
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rresp : std_logic_vector(1 downto 0);
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rlast : std_logic;
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ruser : std_logic_vector(USER_BITS - 1 downto 0);
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rvalid : std_logic;
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end record master_r_in;
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end record master_r_in_t;
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type slave_r_out is record
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type slave_r_out_t is record
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rid : std_logic_vector(RID_SLAVE_BITS - 1 downto 0);
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rdata : std_logic_vector(DATA_BITS - 1 downto 0);
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rresp : std_logic_vector(1 downto 0);
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rlast : std_logic;
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ruser : std_logic_vector(USER_BITS - 1 downto 0);
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rvalid : std_logic;
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end record slave_r_out;
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end record slave_r_out_t;
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type master_r_out is record
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type master_r_out_t is record
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rready : std_logic;
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end record master_r_out;
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end record master_r_out_t;
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subtype slave_r_in is master_r_out;
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subtype slave_r_in is master_r_out_t;
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-- Type declarations for B channel
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type master_b_in is record
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type master_b_in_t is record
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bid : std_logic_vector(WID_MASTER_BITS - 1 downto 0);
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bresp : std_logic_vector(1 downto 0);
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buser : std_logic_vector(USER_BITS - 1 downto 0);
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bvalid : std_logic;
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end record master_b_in;
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end record master_b_in_t;
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type slave_b_out is record
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type slave_b_out_t is record
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bid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0);
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bresp : std_logic_vector(1 downto 0);
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buser : std_logic_vector(USER_BITS - 1 downto 0);
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bvalid : std_logic;
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end record slave_b_out;
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end record slave_b_out_t;
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type master_b_out is record
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type master_b_out_t is record
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bready : std_logic;
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end record master_b_out;
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end record master_b_out_t;
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subtype slave_b_in is master_b_out;
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subtype slave_b_in_t is master_b_out_t;
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-- Combined definitions
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type axi_master_in is record
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aw : master_aw_in;
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ar : master_ar_in;
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w : master_w_in;
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r : master_r_in;
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b : master_b_in;
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end record axi_master_in;
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type axi_master_in_t is record
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aw : master_aw_in_t;
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ar : master_ar_in_t;
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w : master_w_in_t;
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r : master_r_in_t;
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b : master_b_in_t;
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end record axi_master_in_t;
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type axi_master_out is record
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aw : master_aw_out;
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ar : master_ar_out;
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w : master_w_out;
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r : master_r_out;
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b : master_b_out;
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end record axi_master_out;
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type axi_master_out_t is record
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aw : master_aw_out_t;
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ar : master_ar_out_t;
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w : master_w_out_t;
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r : master_r_out_t;
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b : master_b_out_t;
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end record axi_master_out_t;
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type axi_slave_in is record
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aw : slave_aw_in;
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ar : slave_ar_in;
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w : slave_w_in;
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type axi_slave_in_t is record
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aw : slave_aw_in_t;
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ar : slave_ar_in_t;
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w : slave_w_in_t;
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r : slave_r_in;
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b : slave_b_in;
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end record axi_slave_in;
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b : slave_b_in_t;
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end record axi_slave_in_t;
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type axi_slave_out is record
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aw : slave_aw_out;
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type axi_slave_out_t is record
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aw : slave_aw_out_t;
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ar : slave_ar_out;
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w : slave_w_out;
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r : slave_r_out;
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b : slave_b_out;
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end record axi_slave_out;
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r : slave_r_out_t;
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b : slave_b_out_t;
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end record axi_slave_out_t;
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-- Array definitions
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type axi_masters_in is array (natural range <>) of axi_master_in;
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type axi_masters_out is array (natural range <>) of axi_master_out;
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type axi_slaves_in is array (natural range <>) of axi_slave_in;
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type axi_slaves_out is array (natural range <>) of axi_slave_out;
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type axi_masters_in_t is array (natural range <>) of axi_master_in_t;
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type axi_masters_out_t is array (natural range <>) of axi_master_out_t;
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type axi_slaves_in_t is array (natural range <>) of axi_slave_in_t;
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type axi_slaves_out_t is array (natural range <>) of axi_slave_out_t;
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end package axi3intercon_pkg;
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