fpga/axi3-interconnect
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started type definitions

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Mario Hüttel 2016-08-20 14:43:06 +02:00
commit c35444e55a
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.gitignore vendored Normal file
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*~

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.library_mapping.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<com.sigasi.hdt.shared.librarymapping.model:LibraryMappings xmlns:com.sigasi.hdt.shared.librarymapping.model="com.sigasi.hdt.vhdl.scoping.librarymapping" Version="2">
<Mappings Location="src" Library="axi3intercon"/>
<Mappings Location="Common Libraries/IEEE" Library="ieee"/>
<Mappings Location="Common Libraries" Library="not mapped"/>
<Mappings Location="Common Libraries/STD" Library="std"/>
<Mappings Location="" Library="work"/>
</com.sigasi.hdt.shared.librarymapping.model:LibraryMappings>

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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>axi3-interconnect</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.sigasi.hdt.vhdl.ui.vhdlNature</nature>
<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
</natures>
<linkedResources>
<link>
<name>Common Libraries</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt</name>
<type>1</type>
<locationURI>sigasiresource:/vhdl/readme2.txt</locationURI>
</link>
<link>
<name>Common Libraries/IEEE</name>
<type>2</type>
<locationURI>sigasiresource:/vhdl/2008/IEEE</locationURI>
</link>
<link>
<name>Common Libraries/STD</name>
<type>2</type>
<locationURI>sigasiresource:/vhdl/2008/STD</locationURI>
</link>
<link>
<name>Common Libraries/IEEE/Synopsys</name>
<type>2</type>
<locationURI>sigasiresource:/vhdl/2008/IEEE%20Synopsys</locationURI>
</link>
</linkedResources>
</projectDescription>

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.settings/org.eclipse.core.resources.prefs Normal file
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eclipse.preferences.version=1
encoding//Common\ Libraries/IEEE=utf-8
encoding//Common\ Libraries/IEEE/Synopsys=utf-8
encoding//Common\ Libraries/STD=utf-8
encoding/Common\ Libraries=utf-8

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src/axi3-interconnect.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi3intercon is
port (
aclk : in std_logic;
aresetn : in std_logic
);
end entity axi3intercon;
architecture RTL of axi3intercon is
signal rst : std_logic;
begin
reset_sync : process(aclk, aresetn) is
begin
if aresetn = '0' then
rst <= '1';
elsif rising_edge(aclk) then
rst <= '0';
end if;
end process reset_sync;
end architecture RTL;

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src/axi3-interconnect_pkg.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package axi3intercon_pkg is
constant RID_MASTER_BITS : natural := 8;
constant RID_SLAVE_BITS : natural := 10;
constant WID_MASTER_BITS : natural := 8;
constant WID_SLAVE_BITS : natural := 10;
constant DATA_BITS : natural := 32;
constant DATA_STROBES : natural := (DATA_BITS / 8);
constant ADDRESS_BITS : natural := 32;
constant MASTER_COUNT : natural := 2;
constant SLAVE_COUNT : natural := 2;
-- type declarations for AW channel
type master_aw_out is record
awid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); -- Write transaction ID
awaddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write address
awlen : std_logic_vector(7 downto 0); -- Burst length - 1;
awsize : std_logic_vector(2 downto 0); -- Maximum size of the beat
awburst : std_logic_vector(1 downto 0); -- Burst type
awlock : std_logic_vector(1 downto 0); -- Lock info
awcache : std_logic_vector(3 downto 0); -- caching info
awprot : std_logic_vector(2 downto 0); -- protection info
awvalid : std_logic; -- Data valid
end record master_aw_out;
type master_aw_in is record
awready : std_logic;
end record master_aw_in;
type slave_aw_in is record
awid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); -- Write transaction ID
awaddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write address
awlen : std_logic_vector(7 downto 0); -- Burst length - 1;
awsize : std_logic_vector(2 downto 0); -- Maximum size of the beat
awburst : std_logic_vector(1 downto 0); -- Burst type
awlock : std_logic_vector(1 downto 0); -- Lock info
awcache : std_logic_vector(3 downto 0); -- caching info
awprot : std_logic_vector(2 downto 0); -- protection info
awvalid : std_logic; -- Data valid
end record slave_aw_in;
alias slave_aw_out is master_aw_in;
-- type decalatations for AR cahnnel
type master_ar_out is record
arid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); -- Write transaction ID
araddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write start address
arlen : std_logic_vector(7 downto 0); -- Burst length - 1;
arsize : std_logic_vector(2 downto 0); -- Maximum size of the beat
arburst : std_logic_vector(1 downto 0); -- Burst type
arlock : std_logic_vector(1 downto 0); -- Lock info
arcache : std_logic_vector(3 downto 0); -- caching info
arprot : std_logic_vector(2 downto 0); -- protection info
arvalid : std_logic; -- Data valid
end record master_ar_out;
type master_ar_in is record
awready : std_logic;
end record master_ar_in;
type slave_ar_in is record
arid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); -- Read transaction ID
araddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Read start address
arlen : std_logic_vector(7 downto 0); -- Burst length - 1;
arsize : std_logic_vector(2 downto 0); -- Maximum size of the beat
arburst : std_logic_vector(1 downto 0); -- Burst type
arlock : std_logic_vector(1 downto 0); -- Lock info
arcache : std_logic_vector(3 downto 0); -- caching info
arprot : std_logic_vector(2 downto 0); -- protection info
arvalid : std_logic; -- Data valid
end record slave_ar_in;
alias slave_ar_out is master_ar_in;
-- type decalarations for W channel
type master_w_out is record
wid : std_logic_vector(WID_MASTER_BITS - 1 downto 0);
wdata : std_logic_vector(DATA_BITS - 1 downto 0);
wstrb : std_logic_vector(DATA_STROBES - 1 downto 0);
wlast : std_logic;
wuser : std_logic; -- user defined
wvalid : std_logic;
end record master_w_out;
type slave_w_in is record
wid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0);
wdata : std_logic_vector(DATA_BITS - 1 downto 0);
wstrb : std_logic_vector(DATA_STROBES - 1 downto 0);
wlast : std_logic;
wuser : std_logic; -- user defined
wvalid : std_logic;
end record slave_w_in;
type master_w_in is record
wready : std_logic;
end record master_w_in;
alias slave_w_out is master_w_in;
end package axi3intercon_pkg;
package body axi3intercon_pkg is
end package body axi3intercon_pkg;