fpga/axi3-interconnect
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Add reports for simulation and fix errors

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This commit is contained in:
Mario Hüttel 2019-07-28 22:58:10 +02:00
parent 79d90c19f0
commit fffe85f404
4 changed files with 75 additions and 65 deletions
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15
src/axi3-interconnect-decerr.vhd
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@ -52,7 +52,6 @@ begin
begin
if rst = '1' then
r_state <= R_READY;
slave_out.ar.arready <= '0';
slave_out.r.rdata <= (others => '0');
slave_out.r.rid <= (others => '0');
slave_out.r.rlast <= '0';
@ -64,11 +63,12 @@ begin
when R_READY =>
slave_out.r.rlast <= '0';
if slave_in.ar.arvalid = '1' then
report "Decoder error for READ on address detected" severity note;
r_state <= R_ERROR;
slave_out.r.rid <= slave_in.ar.arid;
slave_out.r.rresp <= AXI_RESP_DECERR;
slave_out.r.rvalid <= '1';
if unsigned(slave_in.ar.arlen) = 1 then
if unsigned(slave_in.ar.arlen) = 0 then
slave_out.r.rlast <= '1';
else
slave_out.r.rlast <= '0';
@ -78,13 +78,15 @@ begin
when R_ERROR =>
slave_out.r.rvalid <= '1';
if slave_in.r.rready = '1' then
if r_len /= to_unsigned(0, r_len'length) then
r_len <= r_len - 1;
if r_len = 2 then
slave_out.r.rlast <= '1';
end if;
if r_len = to_unsigned(1, r_len'length) then
else
r_state <= R_READY;
slave_out.r.rvalid <= '0';
slave_out.r.rlast <= '0';
end if;
if r_len = to_unsigned(1, r_len'length) then
slave_out.r.rlast <= '1';
end if;
end if;
end case;
@ -108,6 +110,7 @@ begin
case w_state is
when W_READY =>
if slave_in.w.wvalid = '1' then
report "Decoder error in write transaction" severity note;
w_state <= W_ERROR;
slave_out.b.bid <= slave_in.w.wid;
slave_out.b.bresp <= AXI_RESP_DECERR;

7
src/axi3-interconnect_pkg.vhd
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@ -45,8 +45,8 @@ package axi3intercon_pkg is
constant USER_BITS : natural := 4;
constant MASTER_COUNT : natural := 2;
constant SLAVE_COUNT : natural := 2;
constant MASTER_COUNT : natural := 1;
constant SLAVE_COUNT : natural := 1;
-- Constant definitions for signals
@ -265,6 +265,9 @@ package body axi3intercon_pkg is
slave_idx := i;
end if;
end loop;
report "Calculated slave address: " & integer'image(slave_idx) severity note;
return slave_idx;
end function calculate_slave;

4
src/master2slave/axi3-interconnect-ar-router.vhd
View File

@ -53,6 +53,7 @@ architecture RTL of axi3intercon_ar_router is
signal ar_states : ar_states_t;
signal arready_s : std_logic_vector(0 to MASTER_COUNT - 1);
type slave_indexes_t is array (0 to MASTER_COUNT - 1) of integer range 0 to SLAVE_COUNT;
signal debug_idx : integer range 0 to SLAVE_COUNT;
begin
arready_gen : for i in 0 to MASTER_COUNT - 1 generate
masters_in(i).arready <= arready_s(i);
@ -86,9 +87,10 @@ begin
when AR_READY =>
if masters_out(i).arvalid = '1' then
slave_idx(i) := calculate_slave(masters_out(i).araddr, address_array, mask_array);
debug_idx <= slave_idx(i);
if slave_in_use(slave_idx(i)) /= '1' then
slave_in_use(slave_idx(i)) := '1';
masters_in(i).arready <= '1';
arready_s(i) <= '1';
-- Write request to slave
if slave_idx(i) = SLAVE_COUNT then
slaves_in(slave_idx(i)).araddr <= masters_out(i).araddr;

2
src/master2slave/axi3-interconnect-aw-router.vhd
View File

@ -70,6 +70,8 @@ begin
if rst = '1' then
for i in 0 to MASTER_COUNT - 1 loop
aw_states(i) <= AW_READY;
write_locks_s(i).slave_idx <= 0;
write_locks_s(i).locked <= '0';
end loop;
for i in 0 to SLAVE_COUNT loop
slaves_in(i).awvalid <= '0';