92 lines
3.0 KiB
VHDL
92 lines
3.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- "work" denotes the curent library. Similar to this in C++, C# etc...
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use work.axi3intercon_pkg.all;
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use work.axi_aw_router_pkg.all;
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use work.axi_ar_router_pkg.all;
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entity axi3intercon is
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port(
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aclk : in std_logic;
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aresetn : in std_logic;
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masters_in : out axi_masters_in_t(0 to MASTER_COUNT - 1);
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masters_out : in axi_masters_out_t(0 to MASTER_COUNT - 1);
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slaves_in : out axi_slaves_in_t(0 to SLAVE_COUNT - 1);
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slaves_out : in axi_slaves_out_t(0 to SLAVE_COUNT - 1);
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address_array : axi_slave_addresses_t(0 to SLAVE_COUNT - 1);
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mask_array : axi_slave_addresses_t(0 to SLAVE_COUNT - 1)
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);
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end entity axi3intercon;
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architecture RTL of axi3intercon is
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signal rst : std_logic;
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signal write_locks : write_locks_t(0 to MASTER_COUNT - 1);
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signal write_releases : write_releases_t;
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signal aw_masters_out : axi_aw_masters_out_t(0 to MASTER_COUNT - 1);
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signal aw_masters_in : axi_aw_masters_in_t(0 to MASTER_COUNT - 1);
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signal aw_slaves_out : axi_aw_slaves_out_t(0 to SLAVE_COUNT);
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signal aw_slaves_in : axi_aw_slaves_in_t(0 to SLAVE_COUNT);
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signal ar_masters_out : axi_ar_masters_out_t(0 to MASTER_COUNT - 1);
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signal ar_masters_in : axi_ar_masters_in_t(0 to MASTER_COUNT - 1);
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signal ar_slaves_out : axi_ar_slaves_out_t(0 to SLAVE_COUNT);
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signal ar_slaves_in : axi_ar_slaves_in_t(0 to SLAVE_COUNT);
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begin
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reset_sync : process(aclk, aresetn) is
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begin
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if aresetn = '0' then
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rst <= '1';
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elsif rising_edge(aclk) then
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rst <= '0';
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end if;
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end process reset_sync;
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axi3intercon_aw_router_inst : entity work.axi3intercon_aw_router
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port map(
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aclk => aclk,
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rst => rst,
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masters_out => aw_masters_out,
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masters_in => aw_masters_in,
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slaves_out => aw_slaves_out,
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slaves_in => aw_slaves_in,
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write_locks => write_locks,
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write_releases => write_releases,
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address_array => address_array,
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mask_array => mask_array
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);
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aw_master_connect : for i in 0 to MASTER_COUNT - 1 generate
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aw_masters_out(i) <= masters_out(i).aw;
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masters_in(i).aw <= aw_masters_in(i);
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end generate aw_master_connect;
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aw_slave_connect : for i in 0 to SLAVE_COUNT - 1 generate
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aw_slaves_out(i) <= slaves_out(i).aw;
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slaves_in(i).aw <= aw_slaves_in(i);
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end generate aw_slave_connect;
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axi3intercon_ar_router_inst : entity work.axi3intercon_ar_router
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port map(
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aclk => aclk,
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rst => rst,
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masters_out => ar_masters_out,
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masters_in => ar_masters_in,
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slaves_out => ar_slaves_out,
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slaves_in => ar_slaves_in,
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address_array => address_array,
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mask_array => mask_array
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);
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ar_master_connect : for i in 0 to MASTER_COUNT - 1 generate
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ar_masters_out(i) <= masters_out(i).ar;
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masters_in(i).ar <= ar_masters_in(i);
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end generate ar_master_connect;
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ar_slave_connect : for i in 0 to SLAVE_COUNT - 1 generate
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ar_slaves_out(i) <= slaves_out(i).ar;
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slaves_in(i).ar <= ar_slaves_in(i);
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end generate ar_slave_connect;
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end architecture RTL;
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