wrote w router
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@ -38,7 +38,9 @@ begin
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if rst = '1' then
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for i in 0 to MASTER_COUNT - 1 loop
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ar_states(i) <= AR_READY;
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end loop;
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for i in 0 to SLAVE_COUNT loop
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slaves_in(i).arvalid <= '0';
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end loop;
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slave_in_use := (others => '0');
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arready_s <= (others => '1');
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@ -14,7 +14,7 @@ entity axi3intercon_aw_router is
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slaves_out : in axi_aw_slaves_out_t(0 to SLAVE_COUNT);
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slaves_in : out axi_aw_slaves_in_t(0 to SLAVE_COUNT);
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write_locks : out write_locks_t(0 to MASTER_COUNT - 1); -- write_* signals come/go from/to the write router.
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write_releases : in write_release_t;
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write_releases : in write_releases_t;
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address_array : in axi_slave_addresses_t(0 to SLAVE_COUNT - 1);
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mask_array : in axi_slave_addresses_t(0 to SLAVE_COUNT - 1)
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);
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@ -53,6 +53,9 @@ begin
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for i in 0 to MASTER_COUNT - 1 loop
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aw_states(i) <= AW_READY;
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end loop;
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for i in 0 to SLAVE_COUNT loop
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slaves_in(i).awvalid <= '0';
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end loop;
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awready_s <= (others => '1');
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slave_in_use := (others => '0');
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elsif rising_edge(clk) then
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@ -15,7 +15,7 @@ package axi_aw_router_pkg is
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end record write_lock_t;
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type write_locks_t is array (natural range <>) of write_lock_t;
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subtype write_release_t is std_logic_vector(0 to MASTER_COUNT - 1);
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subtype write_releases_t is std_logic_vector(0 to MASTER_COUNT - 1);
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end package axi_aw_router_pkg;
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78
src/axi3-interconnect-w-router.vhd
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78
src/axi3-interconnect-w-router.vhd
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@ -0,0 +1,78 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.axi3intercon_pkg.all;
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use work.axi_aw_router_pkg.all;
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use work.axi_w_router_pkg.all;
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entity axi3_intercon_w_router is
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port(
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clk : in std_logic;
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rst : in std_logic;
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masters_in : out axi_w_masters_in_t(0 to MASTER_COUNT - 1);
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masters_out : in axi_w_masters_out_t(0 to MASTER_COUNT - 1);
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slaves_in : out axi_w_slaves_in_t(0 to SLAVE_COUNT);
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slaves_out : in axi_w_slaves_out_t(0 to SLAVE_COUNT);
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write_locks : in write_locks_t;
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write_releases : out write_releases_t
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);
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end entity axi3_intercon_w_router;
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architecture RTL of axi3_intercon_w_router is
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type w_state_t is (W_READY, W_ACTIVE);
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type w_states_t is array (0 to MASTER_COUNT - 1) of w_state_t;
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signal w_states : w_states_t;
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signal wready_s : std_logic_vector(0 to MASTER_COUNT - 1);
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begin
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wready_gen : for i in 0 to MASTER_COUNT - 1 generate
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masters_in(i).wready <= wready_s(i);
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end generate wready_gen;
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w_router_sync : process(clk, rst) is
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begin
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if rst = '1' then
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for i in 0 to MASTER_COUNT - 1 loop
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wready_s(i) <= '0';
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write_releases(i) <= '0';
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end loop;
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for i in 0 to SLAVE_COUNT loop
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slaves_in(i).wvalid <= '0';
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end loop;
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elsif rising_edge(clk) then
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for i in 0 to MASTER_COUNT - 1 loop
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write_releases(i) <= '0';
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if write_locks(i).locked = '1' then
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case w_states(i) is
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when W_READY =>
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wready_s(i) <= '1';
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if wready_s(i) = '1' and masters_out(i).wvalid = '1' then
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wready_s(i) <= '0';
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slaves_in(write_locks(i).slave_idx).wdata <= masters_out(i).wdata;
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slaves_in(write_locks(i).slave_idx).wid <= std_logic_vector(to_unsigned(i, WID_SLAVE_BITS - WID_MASTER_BITS)) & masters_out(i).wid;
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slaves_in(write_locks(i).slave_idx).wlast <= masters_out(i).wlast;
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slaves_in(write_locks(i).slave_idx).wstrb <= masters_out(i).wstrb;
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slaves_in(write_locks(i).slave_idx).wuser <= masters_out(i).wuser;
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slaves_in(write_locks(i).slave_idx).wvalid <= '1';
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if masters_out(i).wlast = '1' then
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write_releases(i) <= '1';
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end if;
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w_states(i) <= W_ACTIVE;
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end if;
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when W_ACTIVE =>
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if slaves_out(write_locks(i).slave_idx).wready = '1' then
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slaves_in(write_locks(i).slave_idx).wvalid <= '0';
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w_states(i) <= W_READY;
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end if;
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end case;
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else
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slaves_in(i).wvalid <= '0';
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wready_s(i) <= '0';
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end if;
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end loop;
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end if;
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end process w_router_sync;
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end architecture RTL;
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14
src/axi3-interconnect-w-router_pkg.vhd
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14
src/axi3-interconnect-w-router_pkg.vhd
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@ -0,0 +1,14 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.axi3intercon_pkg.all;
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package axi_w_router_pkg is
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type axi_w_masters_in_t is array (natural range <>) of master_w_in_t;
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type axi_w_masters_out_t is array (natural range <>) of master_w_out_t;
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type axi_w_slaves_out_t is array (natural range <>) of slave_w_out_t;
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type axi_w_slaves_in_t is array (natural range <>) of slave_w_in_t;
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end package axi_w_router_pkg;
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-- package body axi_w_router_pkg is
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-- end package body axi_w_router_pkg;
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@ -22,7 +22,7 @@ end entity axi3intercon;
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architecture RTL of axi3intercon is
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signal rst : std_logic;
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signal write_locks : write_locks_t(0 to MASTER_COUNT - 1);
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signal write_releases : write_release_t;
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signal write_releases : write_releases_t;
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signal aw_masters_out : axi_aw_masters_out_t(0 to MASTER_COUNT - 1);
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signal aw_masters_in : axi_aw_masters_in_t(0 to MASTER_COUNT - 1);
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signal aw_slaves_out : axi_aw_slaves_out_t(0 to SLAVE_COUNT);
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