46 lines
1.2 KiB
VHDL
46 lines
1.2 KiB
VHDL
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-------------------------------------------------------------------------------
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-- Title : MachXO2 Serial Configuration
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-- Project : tiny-xo2
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-------------------------------------------------------------------------------
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-- File : top.vhd
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-- Author : マリオ <mario.huettel@gmx.net>
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-- Company :
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-- Created : 2017-11-21
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-- Last update: 2017-11-21
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2017 GPLv2
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity config_top is
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generic (
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BAUD_RATE : integer := 9600);
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port (
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clk : in std_logic; -- input clock 12 MHz
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dts : in std_logic; -- DTS Strobe signal
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uart_tx : out std_logic; -- UART TX
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uart_rx : in std_logic); -- UART RX
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end entity config_top;
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architecture RTL of config_top is
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begin -- architecture RTL
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end architecture RTL;
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