Mario Hüttel 7dec75c52e timeout counter implemented, starting FSM that controls UART <=> Wishbone transfers		2017-11-23 00:25:09 +01:00
.gitignore	add uart and top vhd	2017-11-21 22:11:53 +01:00
efb_ufr.vhd	fix parity in uart_tx, generate EFB/UFR IP for configuration	2017-11-22 21:42:46 +01:00
synchronizer.vhd	added synchronizer ip for UART, wrote reset detection	2017-11-21 22:48:05 +01:00
top.vhd	timeout counter implemented, starting FSM that controls UART <=> Wishbone transfers	2017-11-23 00:25:09 +01:00
uart_rx.vhd	add uart and top vhd	2017-11-21 22:11:53 +01:00
uart_tx.vhd	fix parity in uart_tx, generate EFB/UFR IP for configuration	2017-11-22 21:42:46 +01:00