fpga/ws2812b-eth
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add power on delay

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This commit is contained in:
Mario Hüttel 2018-04-07 19:44:34 +02:00
parent 0425710537
commit 69d26c3a46
1 changed files with 14 additions and 10 deletions
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24
top.vhd
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@ -37,11 +37,12 @@ end entity top;
architecture RTL of top is architecture RTL of top is
constant DELAYCNTVAL : integer := 100000; -- set to low value for constant DELAYCNTVAL : integer := 100000; -- set to low value for
-- simulation -- simulation
constant STARTUPDELAY : integer := 50000000;
constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00"; constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
type smi_state_t is (IDLE, STROBE); type smi_state_t is (IDLE, STROBE);
type smi_init_state_t is (SMI_POR, RESET, INIT, DELAY, INIT_COMPLETE); type smi_init_state_t is (SMI_POR, SMI_PORDELAY, RESET, INIT, DELAY, INIT_COMPLETE);
type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST); type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST);
type receive_t is (PRE, DESTMAC, HEADER, RECV, WAITFORACK); type receive_t is (PRE, DESTMAC, HEADER, RECV, WAITFORACK);
@ -50,9 +51,8 @@ architecture RTL of top is
signal sendstate : smi_state_t; signal sendstate : smi_state_t;
signal initstate : smi_init_state_t := SMI_POR; signal initstate : smi_init_state_t := SMI_POR;
signal after_delay_state : smi_init_state_t := RESET;
signal rst_rxtx : std_logic; signal rst_rxtx : std_logic;
signal delaycounter : unsigned(19 downto 0); signal delaycounter : unsigned(26 downto 0);
signal smi_reg : std_logic_vector(4 downto 0); signal smi_reg : std_logic_vector(4 downto 0);
signal smi_dat : std_logic_vector(15 downto 0); signal smi_dat : std_logic_vector(15 downto 0);
signal smi_strb : std_logic; signal smi_strb : std_logic;
@ -200,31 +200,35 @@ begin -- architecture RTL
rst_rxtx <= '1'; rst_rxtx <= '1';
initstate <= SMI_POR; initstate <= SMI_POR;
sendstate <= IDLE; sendstate <= IDLE;
after_delay_state <= RESET;
delaycounter <= (others => '0'); delaycounter <= (others => '0');
elsif rising_edge(clk) then elsif rising_edge(clk) then
smi_strb <= '0'; smi_strb <= '0';
rst_rxtx <= '1'; rst_rxtx <= '1';
case initstate is case initstate is
when SMI_POR => when SMI_POR =>
after_delay_state <= RESET;
delaycounter <= (others => '0'); delaycounter <= (others => '0');
initstate <= DELAY; initstate <= SMI_PORDELAY;
when SMI_PORDELAY =>
delaycounter <= delaycounter + 1;
if delaycounter = STARTUPDELAY then
initstate <= RESET;
end if;
when RESET => when RESET =>
after_delay_state <= INIT;
delaycounter <= (others => '0'); delaycounter <= (others => '0');
sendsmi((others => '0'), x"8000", DELAY); sendsmi((others => '0'), x"8000", DELAY);
when DELAY => when DELAY =>
delaycounter <= delaycounter + 1; delaycounter <= delaycounter + 1;
if delaycounter = DELAYCNTVAL then -- Set to 100000 if delaycounter = DELAYCNTVAL then -- Set to 100000
initstate <= after_delay_state; initstate <= INIT;
end if; end if;
when INIT => when INIT =>
sendsmi((others => '0'), "00" & '1' & '1' & "000" & '1' & "00000000", INIT_COMPLETE); sendsmi((others => '0'), "00" & '1' & '1' & "000" & '1' & "00000000", INIT_COMPLETE);
when INIT_COMPLETE => when INIT_COMPLETE =>
initstate <= INIT_COMPLETE; initstate <= INIT_COMPLETE;
rst_rxtx <= '0'; if smi_busy = '0' then
rst_rxtx <= '0';
end if;
end case; end case;
end if; end if;
end process initphy; end process initphy;