reset-sync
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parent
c909e0c703
commit
0425710537
28
top.vhd
28
top.vhd
@ -36,9 +36,9 @@ entity top is
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end entity top;
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architecture RTL of top is
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constant DELAYCNTVAL : integer := 100000; -- set to low value for
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-- simulation
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constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
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constant DELAYCNTVAL : integer := 100000; -- set to low value for
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-- simulation
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constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
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type smi_state_t is (IDLE, STROBE);
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type smi_init_state_t is (SMI_POR, RESET, INIT, DELAY, INIT_COMPLETE);
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@ -88,7 +88,17 @@ architecture RTL of top is
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begin -- architecture RTL
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rst <= not rst_hw;
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reset_sync : process(clk, rst_hw) is
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begin
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if rst_hw = '0' then
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rst <= '1';
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elsif rising_edge(clk) then
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if rst_hw = '1' then
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rst <= '0';
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end if;
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end if;
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end process reset_sync;
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smi_1 : entity work.smi
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generic map (
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@ -198,13 +208,13 @@ begin -- architecture RTL
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case initstate is
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when SMI_POR =>
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after_delay_state <= RESET;
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delaycounter <= (others => '0');
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initstate <= DELAY;
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delaycounter <= (others => '0');
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initstate <= DELAY;
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when RESET =>
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after_delay_state <= INIT;
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delaycounter <= (others => '0');
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sendsmi((others => '0'), x"8000", DELAY);
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delaycounter <= (others => '0');
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sendsmi((others => '0'), x"8000", DELAY);
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when DELAY =>
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delaycounter <= delaycounter + 1;
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if delaycounter = DELAYCNTVAL then -- Set to 100000
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