fpga/ws2812b-eth
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edited simulation files

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This commit is contained in:
Mario Hüttel
2018-04-07 19:09:27 +02:00
parent 9dd10afae1
commit c909e0c703
2 changed files with 66 additions and 56 deletions
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10
bench/test.vhd
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@@ -67,7 +67,7 @@ begin -- architecture bench
rst <= '0';
dv <= '0';
rx <= "00";
wait for 100 us;
wait for 350 us;
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
@@ -104,10 +104,10 @@ begin -- architecture bench
sendRMII(x"AA");
sendRMII(x"55");
-- Send FCS
sendRMII(x"2B");
sendRMII(x"69");
sendRMII(x"4E");
sendRMII(x"A8");
sendRMII(x"3A");
sendRMII(x"97");
sendRMII(x"D9");
sendRMII(x"7A");
-- sendRMII(x"AB");