fpga/ws2812b-eth
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edited simulation files

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This commit is contained in:
Mario Hüttel 2018-04-07 19:09:27 +02:00
parent 9dd10afae1
commit c909e0c703
2 changed files with 66 additions and 56 deletions
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10
bench/test.vhd
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@ -67,7 +67,7 @@ begin -- architecture bench
rst <= '0';
dv <= '0';
rx <= "00";
wait for 100 us;
wait for 350 us;
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
@ -104,10 +104,10 @@ begin -- architecture bench
sendRMII(x"AA");
sendRMII(x"55");
-- Send FCS
sendRMII(x"2B");
sendRMII(x"69");
sendRMII(x"4E");
sendRMII(x"A8");
sendRMII(x"3A");
sendRMII(x"97");
sendRMII(x"D9");
sendRMII(x"7A");
-- sendRMII(x"AB");

22
top.vhd
View File

@ -6,7 +6,7 @@
-- Author : Mario Hüttel <mario.huettel@gmx.net>
-- Company :
-- Created : 2018-04-05
-- Last update: 2018-04-06
-- Last update: 2018-04-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
@ -36,11 +36,12 @@ entity top is
end entity top;
architecture RTL of top is
constant DELAYCNTVAL : integer := 100000;
constant DELAYCNTVAL : integer := 100000; -- set to low value for
-- simulation
constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
type smi_state_t is (IDLE, STROBE);
type smi_init_state_t is (RESET, INIT, DELAY, INIT_COMPLETE);
type smi_init_state_t is (SMI_POR, RESET, INIT, DELAY, INIT_COMPLETE);
type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST);
type receive_t is (PRE, DESTMAC, HEADER, RECV, WAITFORACK);
@ -48,7 +49,8 @@ architecture RTL of top is
signal dat_cnt_s : unsigned(3 downto 0);
signal sendstate : smi_state_t;
signal initstate : smi_init_state_t := RESET;
signal initstate : smi_init_state_t := SMI_POR;
signal after_delay_state : smi_init_state_t := RESET;
signal rst_rxtx : std_logic;
signal delaycounter : unsigned(19 downto 0);
signal smi_reg : std_logic_vector(4 downto 0);
@ -186,19 +188,27 @@ begin -- architecture RTL
smi_dat <= (others => '0');
smi_strb <= '0';
rst_rxtx <= '1';
initstate <= RESET;
initstate <= SMI_POR;
sendstate <= IDLE;
after_delay_state <= RESET;
delaycounter <= (others => '0');
elsif rising_edge(clk) then
smi_strb <= '0';
rst_rxtx <= '1';
case initstate is
when SMI_POR =>
after_delay_state <= RESET;
delaycounter <= (others => '0');
initstate <= DELAY;
when RESET =>
after_delay_state <= INIT;
delaycounter <= (others => '0');
sendsmi((others => '0'), x"8000", DELAY);
when DELAY =>
delaycounter <= delaycounter + 1;
if delaycounter = DELAYCNTVAL then -- Set to 100000
initstate <= INIT;
initstate <= after_delay_state;
end if;
when INIT =>
sendsmi((others => '0'), "00" & '1' & '1' & "000" & '1' & "00000000", INIT_COMPLETE);