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Add input FIFO with TB

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This commit is contained in:
Mario Hüttel
2023-10-08 20:36:53 +02:00
parent a57e5cca13
commit 5151e1685d
11 changed files with 871 additions and 143 deletions
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323
rtl/flacdec_double_mem_fifo.vhd Normal file
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-------------------------------------------------------------------------------
-- Title : FIFO based on two single ported memory instances
-- Project : Shimatta VHDL FLAC decoder
-------------------------------------------------------------------------------
-- File : flacdec_double_mem_fifo.vhd
-- Author : Mario Huettel <mario.huettel@linux.com>
-- Company :
-- Created : 2023-10-06
-- Last update: 2023-10-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a FIFO implementation based on two single ported memory
-- instances, which will allow continuous read/write with minimal arbitration
-- overhead. The memory instances have to be connected externally.
-------------------------------------------------------------------------------
-- Copyright (c) 2023
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flacdec_double_mem_fifo is
generic (
ADDRESS_WIDTH : natural range 2 to 32 := 7; -- Adress width of the whole FIFO memory. Defining the FIFO size
DATA_WIDTH : positive := 8); -- Data width in bits
port (
clk : in std_logic; -- Clock
rst_n : in std_logic; -- Async. low-active reset
----------------------------------------------------------------------
-- MEMORY 0 Connections
----------------------------------------------------------------------
mem0_address : out std_logic_vector(ADDRESS_WIDTH - 2 downto 0);
mem0_write_enable : out std_logic;
mem0_read_enable : out std_logic;
mem0_write_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
mem0_read_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
----------------------------------------------------------------------
-- MEMORY 1 Connections
----------------------------------------------------------------------
mem1_address : out std_logic_vector(ADDRESS_WIDTH - 2 downto 0);
mem1_write_enable : out std_logic;
mem1_read_enable : out std_logic;
mem1_write_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
mem1_read_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
----------------------------------------------------------------------
-- Input AXI Stream
----------------------------------------------------------------------
in_tdata : in std_logic_vector(DATA_WIDTH - 1 downto 0);
in_tvalid : in std_logic;
in_tready : out std_logic;
----------------------------------------------------------------------
-- Output AXI stream
----------------------------------------------------------------------
out_tdata : out std_logic_vector(DATA_WIDTH -1 downto 0);
out_tvalid : out std_logic;
out_tready : in std_logic;
----------------------------------------------------------------------
-- Control and status
----------------------------------------------------------------------
clear : in std_logic;
flush_output : in std_logic;
fill_level : out std_logic_vector(ADDRESS_WIDTH downto 0);
empty : out std_logic;
full : out std_logic;
half_empty : out std_logic);
end entity flacdec_double_mem_fifo;
architecture RTL of flacdec_double_mem_fifo is
constant FIFO_SIZE : natural := 2**ADDRESS_WIDTH;
signal accepted_input_reg : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal accepted_input_valid_reg : std_logic;
signal in_tready_s : std_logic;
signal out_tvalid_reg : std_logic;
signal out_tdata_buffer_reg : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal out_tdata_buffer_valid_reg : std_logic;
signal fifo_read_out_data_s : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal out_ready_for_data_s : std_logic;
signal write_pointer_reg : unsigned(ADDRESS_WIDTH downto 0);
signal read_pointer_reg : unsigned(ADDRESS_WIDTH downto 0);
signal write_address_s : std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
signal read_address_s : std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
signal write_enable : std_logic;
signal read_enable : std_logic;
signal mem0_read_enable_s : std_logic;
signal mem1_read_enable_s : std_logic;
signal write_dest_mem : std_logic;
signal read_source_mem : std_logic;
signal read_data_valid_reg : std_logic_vector(1 downto 0);
signal fifo_full_s : std_logic;
signal fifo_empty_s : std_logic;
signal fifo_half_empty_s : std_logic;
signal fifo_fill_level_s : integer range 0 to FIFO_SIZE;
begin -- architecture RTL
full <= fifo_full_s;
empty <= fifo_empty_s;
half_empty <= fifo_half_empty_s;
fill_level <= std_logic_vector(to_unsigned(fifo_fill_level_s, fill_level'length));
in_tready <= in_tready_s;
out_tvalid <= out_tvalid_reg;
mem0_read_enable <= mem0_read_enable_s;
mem1_read_enable <= mem1_read_enable_s;
mem0_address <= write_address_s(write_address_s'high downto 1) when mem0_read_enable_s = '0' else read_address_s(read_address_s'high downto 1);
mem1_address <= write_address_s(write_address_s'high downto 1) when mem1_read_enable_s = '0' else read_address_s(read_address_s'high downto 1);
-------------------------------------------------------------------------------------------------------------------------------------------------
-- Writing end implementation
-------------------------------------------------------------------------------------------------------------------------------------------------
write_address_s <= std_logic_vector(write_pointer_reg(write_pointer_reg'high - 1 downto 0));
-- Let LSB decide which memory to write to
write_dest_mem <= write_pointer_reg(0);
mem0_write_enable <= write_enable when write_dest_mem = '0' else '0';
mem1_write_enable <= write_enable when write_dest_mem = '1' else '0';
mem0_write_data <= accepted_input_reg;
mem1_write_data <= accepted_input_reg;
write_enable_proc : process(accepted_input_valid_reg, write_dest_mem, mem0_read_enable_s, mem1_read_enable_s, fifo_full_s) is
begin
write_enable <= '0';
-- Perform write if write destination does not collide with current
-- read (This basically implements the arbitration between read and
-- write, giving priority to the read path).
if (write_dest_mem = '0' and mem0_read_enable_s = '0') or (write_dest_mem = '1' and mem1_read_enable_s = '0') then
-- Write if data is available and the FIFO may take new data
if accepted_input_valid_reg = '1' and fifo_full_s = '0' then
write_enable <= '1';
end if;
end if;
end process write_enable_proc;
-- Write pointer increment upon write action
write_pointer_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
write_pointer_reg <= (others => '0');
elsif rising_edge(clk) then
if clear = '1' then
write_pointer_reg <= (others => '0');
elsif write_enable = '1' then
-- Overflow expected
write_pointer_reg <= write_pointer_reg + 1;
end if;
end if;
end process write_pointer_proc;
-----------------------------------------------------------------
-- AXI input
----------------------------------------------------------------
-- Generate the ready signal for the input stream
axi_input_ready_proc : process(accepted_input_valid_reg, write_enable, clear) is
begin
in_tready_s <= '0';
if accepted_input_valid_reg = '0' then
in_tready_s <= '1';
end if;
if write_enable = '1' then
in_tready_s <= '1';
end if;
if clear = '1' then
in_tready_s <= '0';
end if;
end process axi_input_ready_proc;
-- Accept the input datum into a FF buffer
axi_input_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
accepted_input_reg <= (others => '0');
accepted_input_valid_reg <= '0';
elsif rising_edge(clk) then
if write_enable = '1' or clear = '1' then
-- Reset input buffer once datum is written to memory
accepted_input_valid_reg <= '0';
end if;
if in_tvalid = '1' and in_tready_s = '1' then
-- Accept datum in buffer
accepted_input_valid_reg <= '1';
accepted_input_reg <= in_tdata;
end if;
end if;
end process axi_input_proc;
------------------------------------------------------------------------
-- FIFO status calculations
------------------------------------------------------------------------
fill_level_proc : process(read_pointer_reg, write_pointer_reg) is
variable wrapped_around : boolean;
variable read_addr : integer range 0 to FIFO_SIZE - 1;
variable write_addr : integer range 0 to FIFO_SIZE - 1;
begin
wrapped_around := (read_pointer_reg(read_pointer_reg'high) /= write_pointer_reg(write_pointer_reg'high));
write_addr := to_integer(write_pointer_reg(write_pointer_reg'high - 1 downto 0));
read_addr := to_integer(read_pointer_reg(read_pointer_reg'high -1 downto 0));
if not wrapped_around then
fifo_fill_level_s <= write_addr - read_addr;
else
fifo_fill_level_s <= FIFO_SIZE - read_addr + write_addr;
end if;
end process fill_level_proc;
fifo_full_s <= '1' when write_address_s = read_address_s and read_pointer_reg(read_pointer_reg'high) /= write_pointer_reg(write_pointer_reg'high) else '0';
fifo_empty_s <= '1' when write_pointer_reg = read_pointer_reg else '0';
fifo_half_empty_s <= '1' when fifo_fill_level_s <= FIFO_SIZE / 2 else '0';
-----------------------------------------------------------------------------------------------------------------------------------------------
-- READ end implementation
-----------------------------------------------------------------------------------------------------------------------------------------------
read_address_s <= std_logic_vector(read_pointer_reg(read_pointer_reg'high - 1 downto 0));
read_source_mem <= read_address_s(0);
mem0_read_enable_s <= read_enable when read_source_mem = '0' else '0';
mem1_read_enable_s <= read_enable when read_source_mem = '1' else '0';
read_data_valid_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
read_data_valid_reg <= (others => '0');
elsif rising_edge(clk) then
-- Delay read enables by one cycle, generating a valid signal
read_data_valid_reg <= mem1_read_enable_s & mem0_read_enable_s;
end if;
end process read_data_valid_proc;
-- Generate the read_enable signal
-- Read from fifo if it is not empty and the output is able to accept a new
-- datum. If clear is set, no read is requested.
read_enable_proc : process(fifo_empty_s, out_ready_for_data_s, clear) is
begin
read_enable <= '0';
if fifo_empty_s = '0' and clear = '0' then
if out_ready_for_data_s = '1' then
read_enable <= '1';
end if;
end if;
end process read_enable_proc;
read_pointer_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
read_pointer_reg <= (others => '0');
elsif rising_edge(clk) then
if clear = '1' then
read_pointer_reg <= (others => '0');
elsif read_enable = '1' then
-- Overflow expected
read_pointer_reg <= read_pointer_reg + 1;
end if;
end if;
end process read_pointer_proc;
--------------------
-- Output AXI stream
---------------------
-- Read data mux
fifo_read_out_data_s <= mem0_read_data when read_data_valid_reg(0) = '1' else mem1_read_data;
-- Determine if output flops can be loaded with new data
out_ready_for_data_s <= (not out_tvalid_reg) or out_tready;
axi_output_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
out_tvalid_reg <= '0';
out_tdata <= (others => '0');
out_tdata_buffer_valid_reg <= '0';
out_tdata_buffer_reg <= (others => '0');
elsif rising_edge(clk) then
if out_tready = '1' then
out_tvalid_reg <= '0';
end if;
if flush_output = '1' then
-- Flush the output. This breaks the stream protocol!
out_tvalid_reg <= '0';
out_tdata_buffer_valid_reg <= '0';
else -- Output is not flushed
if out_ready_for_data_s = '1' then
if out_tdata_buffer_valid_reg = '1' then
out_tdata <= out_tdata_buffer_reg;
out_tvalid_reg <= '1';
out_tdata_buffer_valid_reg <= '0';
elsif read_data_valid_reg /= "00" then
out_tdata <= fifo_read_out_data_s;
out_tvalid_reg <= '1';
end if;
end if;
-- Fill buffer register, if output is not ready for data or
-- filled with old buffer data
if read_data_valid_reg /= "00" and ((out_ready_for_data_s = '1' and out_tdata_buffer_valid_reg = '1') or out_ready_for_data_s = '0') then
out_tdata_buffer_reg <= fifo_read_out_data_s;
out_tdata_buffer_valid_reg <= '1';
end if;
end if;
end if;
end process axi_output_proc;
end architecture RTL;

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rtl/flacdec_input_fifo.vhd Normal file
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-------------------------------------------------------------------------------
-- Title : Input FIFO for FLAC data
-- Project : Shimatta VHDL FLAC decoder
-------------------------------------------------------------------------------
-- File : flacdec_input_fifo.vhd
-- Author : Mario Huettel <mario.huettel@linux.com>
-- Company :
-- Created : 2023-10-07
-- Last update: 2023-10-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: 128 byte input FIFO of FLAC core
-------------------------------------------------------------------------------
-- Copyright (c) 2023
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flacdec_input_fifo is
port (
clk : in std_logic; -- CLock
rst_n : in std_logic; -- async. low-active reset
------------------------------------------------
-- Input AXI stream
------------------------------------------------
in_tdata : in std_logic_vector(7 downto 0);
in_tvalid : in std_logic;
in_tready : out std_logic;
------------------------------------------------
-- Output AXI Stream
------------------------------------------------
out_tdata : out std_logic_vector(7 downto 0);
out_tvalid : out std_logic;
out_tready : in std_logic;
------------------------------------------------
-- Control and status signals
------------------------------------------------
clear : in std_logic;
half_empty : out std_logic;
empty : out std_logic;
full : out std_logic;
flush_output : in std_logic);
end entity flacdec_input_fifo;
architecture RTL of flacdec_input_fifo is
constant ADDRESS_WIDTH : natural := 7;
constant DATA_WIDTH : natural := 8;
signal mem0_address : std_logic_vector(ADDRESS_WIDTH - 2 downto 0);
signal mem0_write_enable : std_logic;
signal mem0_read_enable : std_logic;
signal mem0_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem0_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem1_address : std_logic_vector(ADDRESS_WIDTH - 2 downto 0);
signal mem1_write_enable : std_logic;
signal mem1_read_enable : std_logic;
signal mem1_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem1_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
begin -- architecture RTL
-- FIFO logic core
flacdec_double_mem_fifo_1 : entity work.flacdec_double_mem_fifo
generic map (
ADDRESS_WIDTH => ADDRESS_WIDTH,
DATA_WIDTH => DATA_WIDTH)
port map (
clk => clk,
rst_n => rst_n,
mem0_address => mem0_address,
mem0_write_enable => mem0_write_enable,
mem0_read_enable => mem0_read_enable,
mem0_write_data => mem0_write_data,
mem0_read_data => mem0_read_data,
mem1_address => mem1_address,
mem1_write_enable => mem1_write_enable,
mem1_read_enable => mem1_read_enable,
mem1_write_data => mem1_write_data,
mem1_read_data => mem1_read_data,
in_tdata => in_tdata,
in_tvalid => in_tvalid,
in_tready => in_tready,
out_tdata => out_tdata,
out_tvalid => out_tvalid,
out_tready => out_tready,
clear => clear,
flush_output => flush_output,
fill_level => open,
empty => empty,
full => full,
half_empty => half_empty);
---------------------------------------------------------------
-- Memory instances
---------------------------------------------------------------
flacdec_64x08_memory_i0 : entity work.flacdec_64x08_memory
port map (
clk => clk,
address => mem0_address,
write_enable => mem0_write_enable,
read_enable => mem0_read_enable,
write_data => mem0_write_data,
read_data => mem0_read_data);
flacdec_64x08_memory_i1 : entity work.flacdec_64x08_memory
port map (
clk => clk,
address => mem1_address,
write_enable => mem1_write_enable,
read_enable => mem1_read_enable,
write_data => mem1_write_data,
read_data => mem1_read_data);
end architecture RTL;

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rtl/mem/flacdec_64x08_memory.vhd Normal file
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-------------------------------------------------------------------------------
-- Title : 64x08 byte single port memory
-- Project : Shimatta VHDL FLAC Decoder
-------------------------------------------------------------------------------
-- File : flacdec_64x08_memory.vhd
-- Author : Mario Huettel <mario.huettel@linux.com>
-- Company : Shimatta
-- Created : 2023-10-06
-- Last update: 2023-10-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a 64 byte single ported RAM implementation. This file
-- should be able to infer a BRAM on FPGA targets.
-- Swap this implementation on an ASIC flow in order to instantiate a fitting
-- memory instance.
-- Two instances of this memory are used in the input FIFO of the Flac decoder
-------------------------------------------------------------------------------
-- Copyright (c) 2023
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flacdec_64x08_memory is
port (
clk : in std_logic; -- Clock
address : in std_logic_vector(5 downto 0); -- RAM data address
write_enable : in std_logic; -- Write enable
read_enable : in std_logic; -- Enable readout
write_data : in std_logic_vector(7 downto 0); -- Write data
read_data : out std_logic_vector(7 downto 0)); -- Read data
end entity flacdec_64x08_memory;
architecture RTL of flacdec_64x08_memory is
type memory_arr_t is array(natural range <>) of std_logic_vector(7 downto 0);
signal mem : memory_arr_t(0 to 63); -- Memory array
signal addr_s : integer range 0 to 63; -- Memory access address
begin -- architecture RTL
addr_s <= to_integer(unsigned(address));
memory_proc : process is
begin
wait until rising_edge(clk);
if write_enable = '1' then
mem(addr_s) <= write_data;
end if;
if read_enable = '1' then
read_data <= mem(addr_s);
end if;
end process memory_proc;
end architecture RTL;

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rtl/mem/flacdec_byte_fifo.vhd
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-------------------------------------------------------------------------------
-- Title : FIFO for 8 bit data
-- Project : VHDL FLAC Decoder
-------------------------------------------------------------------------------
-- File : flacdec_byte_fifo.vhd
-- Author : Mario Huettel <mario.huettel@linux.com>
-- Company :
-- Created : 2023-10-05
-- Last update: 2023-10-05
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a generic FIFO implementation for 8 bit Data. This
-- implementation should be able to map to a dual ported BRAM in an FPGA. If an
-- ASIC Design is used, decide weather to use a RAM instance or let the
-- synthesis generate a FIFO out of Flip Flops.
-- The FIFO is 64 bytes large.
-------------------------------------------------------------------------------
-- Copyright (c) 2023 Mario Huettel
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flacdec_byte_fifo is
port (
clk : in std_logic; -- Clock
rst_n : in std_logic; -- async. low-active reset
data_in : in std_logic_vector(7 downto 0);
data_in_wstrb : in std_logic; -- Write strobe to push data into the FIFO
data_out : out std_logic_vector(7 downto 0); -- Output data. 1 cycle delayed after read strobe.
data_rstrb : in std_logic;
fifo_full : out std_logic; -- FIFO is full
fifo_empty : out std_logic; -- FIFO is empty
fifo_32_free : out std_logic); -- FIFO has at least 32 bytes free
end entity flacdec_byte_fifo;
architecture RTL of flacdec_byte_fifo is
type fifo_mem_t is array(natural range <>) of std_logic_vector(data_in'range);
signal mem : fifo_mem_t(0 to 63);
signal read_ptr : unsigned(6 downto 0);
signal write_ptr : unsigned(6 downto 0);
signal write_strb_s : std_logic;
signal read_strb_s : std_logic;
signal write_addr : unsigned(5 downto 0);
signal read_addr : unsigned(5 downto 0);
signal fifo_fill_level : integer range 0 to 64;
signal wrapped_around : std_logic;
signal fifo_full_s : std_logic;
signal fifo_empty_s : std_logic;
begin -- architecture RTL
fifo_full <= fifo_full_s;
fifo_empty <= fifo_empty_s;
--------------------------------------------------------------------------
-- FIFO memory implementation
--------------------------------------------------------------------------
-- FIFO memory process. Should allow BRAM infer.
fifo_mem_proc : process is
begin
wait until rising_edge(clk);
if write_strb_s = '1' then
mem(to_integer(write_addr)) <= data_in;
end if;
if read_strb_s = '1' then
data_out <= mem(to_integer(read_addr));
end if;
end process fifo_mem_proc;
--------------------------------------------------------------------------
-- FIFO fill level and address logic
--------------------------------------------------------------------------
-- Addresses to memory are the pointers except for the MSB, which is used
-- for wrap around detection
read_addr <= read_ptr(read_ptr'high - 1 downto read_ptr'low);
write_addr <= write_ptr(write_ptr'high - 1 downto write_ptr'low);
wrapped_around <= '1' when read_ptr(read_ptr'high) /= write_ptr(write_ptr'high) else '0';
fill_level_proc : process(wrapped_around, read_addr, write_addr) is
begin
fifo_fill_level <= 0;
if wrapped_around = '0' then
fifo_fill_level <= to_integer(write_addr - read_addr);
else
fifo_fill_level <= to_integer(64 - read_addr + write_addr);
end if;
end process fill_level_proc;
fifo_full_s <= '1' when read_addr = write_addr and wrapped_around = '1' else '0';
fifo_empty_s <= '1' when read_addr = write_addr and wrapped_around = '0' else '0';
fifo_32_free <= '1' when fifo_fill_level >= 32 else '0';
---------------------------------------------------------------------------
-- FIFO write pointer
---------------------------------------------------------------------------
write_strb_s <= data_in_wstrb and (not fifo_full_s);
write_ptr_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
write_ptr <= (others => '0');
elsif rising_edge(clk) then
if write_strb_s = '1' then
-- Wrap around expected
write_ptr <= write_ptr + 1;
end if;
end if;
end process write_ptr_proc;
---------------------------------------------------------------------------
-- FIFO read pointer
---------------------------------------------------------------------------
read_strb_s <= data_rstrb and (not fifo_empty_s);
read_ptr_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
read_ptr <= (others => '0');
elsif rising_edge(clk) then
if read_strb_s = '1' then
-- Wrap around expected
read_ptr <= read_ptr + 1;
end if;
end if;
end process read_ptr_proc;
end architecture RTL;