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Add input FIFO with TB

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Mario Hüttel 2023-10-08 20:36:53 +02:00
parent a57e5cca13
commit 5151e1685d
11 changed files with 871 additions and 143 deletions
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323
rtl/flacdec_double_mem_fifo.vhd Normal file
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-------------------------------------------------------------------------------
-- Title : FIFO based on two single ported memory instances
-- Project : Shimatta VHDL FLAC decoder
-------------------------------------------------------------------------------
-- File : flacdec_double_mem_fifo.vhd
-- Author : Mario Huettel <mario.huettel@linux.com>
-- Company :
-- Created : 2023-10-06
-- Last update: 2023-10-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a FIFO implementation based on two single ported memory
-- instances, which will allow continuous read/write with minimal arbitration
-- overhead. The memory instances have to be connected externally.
-------------------------------------------------------------------------------
-- Copyright (c) 2023
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flacdec_double_mem_fifo is
generic (
ADDRESS_WIDTH : natural range 2 to 32 := 7; -- Adress width of the whole FIFO memory. Defining the FIFO size
DATA_WIDTH : positive := 8); -- Data width in bits
port (
clk : in std_logic; -- Clock
rst_n : in std_logic; -- Async. low-active reset
----------------------------------------------------------------------
-- MEMORY 0 Connections
----------------------------------------------------------------------
mem0_address : out std_logic_vector(ADDRESS_WIDTH - 2 downto 0);
mem0_write_enable : out std_logic;
mem0_read_enable : out std_logic;
mem0_write_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
mem0_read_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
----------------------------------------------------------------------
-- MEMORY 1 Connections
----------------------------------------------------------------------
mem1_address : out std_logic_vector(ADDRESS_WIDTH - 2 downto 0);
mem1_write_enable : out std_logic;
mem1_read_enable : out std_logic;
mem1_write_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
mem1_read_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
----------------------------------------------------------------------
-- Input AXI Stream
----------------------------------------------------------------------
in_tdata : in std_logic_vector(DATA_WIDTH - 1 downto 0);
in_tvalid : in std_logic;
in_tready : out std_logic;
----------------------------------------------------------------------
-- Output AXI stream
----------------------------------------------------------------------
out_tdata : out std_logic_vector(DATA_WIDTH -1 downto 0);
out_tvalid : out std_logic;
out_tready : in std_logic;
----------------------------------------------------------------------
-- Control and status
----------------------------------------------------------------------
clear : in std_logic;
flush_output : in std_logic;
fill_level : out std_logic_vector(ADDRESS_WIDTH downto 0);
empty : out std_logic;
full : out std_logic;
half_empty : out std_logic);
end entity flacdec_double_mem_fifo;
architecture RTL of flacdec_double_mem_fifo is
constant FIFO_SIZE : natural := 2**ADDRESS_WIDTH;
signal accepted_input_reg : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal accepted_input_valid_reg : std_logic;
signal in_tready_s : std_logic;
signal out_tvalid_reg : std_logic;
signal out_tdata_buffer_reg : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal out_tdata_buffer_valid_reg : std_logic;
signal fifo_read_out_data_s : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal out_ready_for_data_s : std_logic;
signal write_pointer_reg : unsigned(ADDRESS_WIDTH downto 0);
signal read_pointer_reg : unsigned(ADDRESS_WIDTH downto 0);
signal write_address_s : std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
signal read_address_s : std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
signal write_enable : std_logic;
signal read_enable : std_logic;
signal mem0_read_enable_s : std_logic;
signal mem1_read_enable_s : std_logic;
signal write_dest_mem : std_logic;
signal read_source_mem : std_logic;
signal read_data_valid_reg : std_logic_vector(1 downto 0);
signal fifo_full_s : std_logic;
signal fifo_empty_s : std_logic;
signal fifo_half_empty_s : std_logic;
signal fifo_fill_level_s : integer range 0 to FIFO_SIZE;
begin -- architecture RTL
full <= fifo_full_s;
empty <= fifo_empty_s;
half_empty <= fifo_half_empty_s;
fill_level <= std_logic_vector(to_unsigned(fifo_fill_level_s, fill_level'length));
in_tready <= in_tready_s;
out_tvalid <= out_tvalid_reg;
mem0_read_enable <= mem0_read_enable_s;
mem1_read_enable <= mem1_read_enable_s;
mem0_address <= write_address_s(write_address_s'high downto 1) when mem0_read_enable_s = '0' else read_address_s(read_address_s'high downto 1);
mem1_address <= write_address_s(write_address_s'high downto 1) when mem1_read_enable_s = '0' else read_address_s(read_address_s'high downto 1);
-------------------------------------------------------------------------------------------------------------------------------------------------
-- Writing end implementation
-------------------------------------------------------------------------------------------------------------------------------------------------
write_address_s <= std_logic_vector(write_pointer_reg(write_pointer_reg'high - 1 downto 0));
-- Let LSB decide which memory to write to
write_dest_mem <= write_pointer_reg(0);
mem0_write_enable <= write_enable when write_dest_mem = '0' else '0';
mem1_write_enable <= write_enable when write_dest_mem = '1' else '0';
mem0_write_data <= accepted_input_reg;
mem1_write_data <= accepted_input_reg;
write_enable_proc : process(accepted_input_valid_reg, write_dest_mem, mem0_read_enable_s, mem1_read_enable_s, fifo_full_s) is
begin
write_enable <= '0';
-- Perform write if write destination does not collide with current
-- read (This basically implements the arbitration between read and
-- write, giving priority to the read path).
if (write_dest_mem = '0' and mem0_read_enable_s = '0') or (write_dest_mem = '1' and mem1_read_enable_s = '0') then
-- Write if data is available and the FIFO may take new data
if accepted_input_valid_reg = '1' and fifo_full_s = '0' then
write_enable <= '1';
end if;
end if;
end process write_enable_proc;
-- Write pointer increment upon write action
write_pointer_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
write_pointer_reg <= (others => '0');
elsif rising_edge(clk) then
if clear = '1' then
write_pointer_reg <= (others => '0');
elsif write_enable = '1' then
-- Overflow expected
write_pointer_reg <= write_pointer_reg + 1;
end if;
end if;
end process write_pointer_proc;
-----------------------------------------------------------------
-- AXI input
----------------------------------------------------------------
-- Generate the ready signal for the input stream
axi_input_ready_proc : process(accepted_input_valid_reg, write_enable, clear) is
begin
in_tready_s <= '0';
if accepted_input_valid_reg = '0' then
in_tready_s <= '1';
end if;
if write_enable = '1' then
in_tready_s <= '1';
end if;
if clear = '1' then
in_tready_s <= '0';
end if;
end process axi_input_ready_proc;
-- Accept the input datum into a FF buffer
axi_input_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
accepted_input_reg <= (others => '0');
accepted_input_valid_reg <= '0';
elsif rising_edge(clk) then
if write_enable = '1' or clear = '1' then
-- Reset input buffer once datum is written to memory
accepted_input_valid_reg <= '0';
end if;
if in_tvalid = '1' and in_tready_s = '1' then
-- Accept datum in buffer
accepted_input_valid_reg <= '1';
accepted_input_reg <= in_tdata;
end if;
end if;
end process axi_input_proc;
------------------------------------------------------------------------
-- FIFO status calculations
------------------------------------------------------------------------
fill_level_proc : process(read_pointer_reg, write_pointer_reg) is
variable wrapped_around : boolean;
variable read_addr : integer range 0 to FIFO_SIZE - 1;
variable write_addr : integer range 0 to FIFO_SIZE - 1;
begin
wrapped_around := (read_pointer_reg(read_pointer_reg'high) /= write_pointer_reg(write_pointer_reg'high));
write_addr := to_integer(write_pointer_reg(write_pointer_reg'high - 1 downto 0));
read_addr := to_integer(read_pointer_reg(read_pointer_reg'high -1 downto 0));
if not wrapped_around then
fifo_fill_level_s <= write_addr - read_addr;
else
fifo_fill_level_s <= FIFO_SIZE - read_addr + write_addr;
end if;
end process fill_level_proc;
fifo_full_s <= '1' when write_address_s = read_address_s and read_pointer_reg(read_pointer_reg'high) /= write_pointer_reg(write_pointer_reg'high) else '0';
fifo_empty_s <= '1' when write_pointer_reg = read_pointer_reg else '0';
fifo_half_empty_s <= '1' when fifo_fill_level_s <= FIFO_SIZE / 2 else '0';
-----------------------------------------------------------------------------------------------------------------------------------------------
-- READ end implementation
-----------------------------------------------------------------------------------------------------------------------------------------------
read_address_s <= std_logic_vector(read_pointer_reg(read_pointer_reg'high - 1 downto 0));
read_source_mem <= read_address_s(0);
mem0_read_enable_s <= read_enable when read_source_mem = '0' else '0';
mem1_read_enable_s <= read_enable when read_source_mem = '1' else '0';
read_data_valid_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
read_data_valid_reg <= (others => '0');
elsif rising_edge(clk) then
-- Delay read enables by one cycle, generating a valid signal
read_data_valid_reg <= mem1_read_enable_s & mem0_read_enable_s;
end if;
end process read_data_valid_proc;
-- Generate the read_enable signal
-- Read from fifo if it is not empty and the output is able to accept a new
-- datum. If clear is set, no read is requested.
read_enable_proc : process(fifo_empty_s, out_ready_for_data_s, clear) is
begin
read_enable <= '0';
if fifo_empty_s = '0' and clear = '0' then
if out_ready_for_data_s = '1' then
read_enable <= '1';
end if;
end if;
end process read_enable_proc;
read_pointer_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
read_pointer_reg <= (others => '0');
elsif rising_edge(clk) then
if clear = '1' then
read_pointer_reg <= (others => '0');
elsif read_enable = '1' then
-- Overflow expected
read_pointer_reg <= read_pointer_reg + 1;
end if;
end if;
end process read_pointer_proc;
--------------------
-- Output AXI stream
---------------------
-- Read data mux
fifo_read_out_data_s <= mem0_read_data when read_data_valid_reg(0) = '1' else mem1_read_data;
-- Determine if output flops can be loaded with new data
out_ready_for_data_s <= (not out_tvalid_reg) or out_tready;
axi_output_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
out_tvalid_reg <= '0';
out_tdata <= (others => '0');
out_tdata_buffer_valid_reg <= '0';
out_tdata_buffer_reg <= (others => '0');
elsif rising_edge(clk) then
if out_tready = '1' then
out_tvalid_reg <= '0';
end if;
if flush_output = '1' then
-- Flush the output. This breaks the stream protocol!
out_tvalid_reg <= '0';
out_tdata_buffer_valid_reg <= '0';
else -- Output is not flushed
if out_ready_for_data_s = '1' then
if out_tdata_buffer_valid_reg = '1' then
out_tdata <= out_tdata_buffer_reg;
out_tvalid_reg <= '1';
out_tdata_buffer_valid_reg <= '0';
elsif read_data_valid_reg /= "00" then
out_tdata <= fifo_read_out_data_s;
out_tvalid_reg <= '1';
end if;
end if;
-- Fill buffer register, if output is not ready for data or
-- filled with old buffer data
if read_data_valid_reg /= "00" and ((out_ready_for_data_s = '1' and out_tdata_buffer_valid_reg = '1') or out_ready_for_data_s = '0') then
out_tdata_buffer_reg <= fifo_read_out_data_s;
out_tdata_buffer_valid_reg <= '1';
end if;
end if;
end if;
end process axi_output_proc;
end architecture RTL;

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rtl/flacdec_input_fifo.vhd Normal file
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-------------------------------------------------------------------------------
-- Title : Input FIFO for FLAC data
-- Project : Shimatta VHDL FLAC decoder
-------------------------------------------------------------------------------
-- File : flacdec_input_fifo.vhd
-- Author : Mario Huettel <mario.huettel@linux.com>
-- Company :
-- Created : 2023-10-07
-- Last update: 2023-10-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: 128 byte input FIFO of FLAC core
-------------------------------------------------------------------------------
-- Copyright (c) 2023
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flacdec_input_fifo is
port (
clk : in std_logic; -- CLock
rst_n : in std_logic; -- async. low-active reset
------------------------------------------------
-- Input AXI stream
------------------------------------------------
in_tdata : in std_logic_vector(7 downto 0);
in_tvalid : in std_logic;
in_tready : out std_logic;
------------------------------------------------
-- Output AXI Stream
------------------------------------------------
out_tdata : out std_logic_vector(7 downto 0);
out_tvalid : out std_logic;
out_tready : in std_logic;
------------------------------------------------
-- Control and status signals
------------------------------------------------
clear : in std_logic;
half_empty : out std_logic;
empty : out std_logic;
full : out std_logic;
flush_output : in std_logic);
end entity flacdec_input_fifo;
architecture RTL of flacdec_input_fifo is
constant ADDRESS_WIDTH : natural := 7;
constant DATA_WIDTH : natural := 8;
signal mem0_address : std_logic_vector(ADDRESS_WIDTH - 2 downto 0);
signal mem0_write_enable : std_logic;
signal mem0_read_enable : std_logic;
signal mem0_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem0_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem1_address : std_logic_vector(ADDRESS_WIDTH - 2 downto 0);
signal mem1_write_enable : std_logic;
signal mem1_read_enable : std_logic;
signal mem1_write_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal mem1_read_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
begin -- architecture RTL
-- FIFO logic core
flacdec_double_mem_fifo_1 : entity work.flacdec_double_mem_fifo
generic map (
ADDRESS_WIDTH => ADDRESS_WIDTH,
DATA_WIDTH => DATA_WIDTH)
port map (
clk => clk,
rst_n => rst_n,
mem0_address => mem0_address,
mem0_write_enable => mem0_write_enable,
mem0_read_enable => mem0_read_enable,
mem0_write_data => mem0_write_data,
mem0_read_data => mem0_read_data,
mem1_address => mem1_address,
mem1_write_enable => mem1_write_enable,
mem1_read_enable => mem1_read_enable,
mem1_write_data => mem1_write_data,
mem1_read_data => mem1_read_data,
in_tdata => in_tdata,
in_tvalid => in_tvalid,
in_tready => in_tready,
out_tdata => out_tdata,
out_tvalid => out_tvalid,
out_tready => out_tready,
clear => clear,
flush_output => flush_output,
fill_level => open,
empty => empty,
full => full,
half_empty => half_empty);
---------------------------------------------------------------
-- Memory instances
---------------------------------------------------------------
flacdec_64x08_memory_i0 : entity work.flacdec_64x08_memory
port map (
clk => clk,
address => mem0_address,
write_enable => mem0_write_enable,
read_enable => mem0_read_enable,
write_data => mem0_write_data,
read_data => mem0_read_data);
flacdec_64x08_memory_i1 : entity work.flacdec_64x08_memory
port map (
clk => clk,
address => mem1_address,
write_enable => mem1_write_enable,
read_enable => mem1_read_enable,
write_data => mem1_write_data,
read_data => mem1_read_data);
end architecture RTL;

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rtl/mem/flacdec_64x08_memory.vhd Normal file
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-------------------------------------------------------------------------------
-- Title : 64x08 byte single port memory
-- Project : Shimatta VHDL FLAC Decoder
-------------------------------------------------------------------------------
-- File : flacdec_64x08_memory.vhd
-- Author : Mario Huettel <mario.huettel@linux.com>
-- Company : Shimatta
-- Created : 2023-10-06
-- Last update: 2023-10-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a 64 byte single ported RAM implementation. This file
-- should be able to infer a BRAM on FPGA targets.
-- Swap this implementation on an ASIC flow in order to instantiate a fitting
-- memory instance.
-- Two instances of this memory are used in the input FIFO of the Flac decoder
-------------------------------------------------------------------------------
-- Copyright (c) 2023
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flacdec_64x08_memory is
port (
clk : in std_logic; -- Clock
address : in std_logic_vector(5 downto 0); -- RAM data address
write_enable : in std_logic; -- Write enable
read_enable : in std_logic; -- Enable readout
write_data : in std_logic_vector(7 downto 0); -- Write data
read_data : out std_logic_vector(7 downto 0)); -- Read data
end entity flacdec_64x08_memory;
architecture RTL of flacdec_64x08_memory is
type memory_arr_t is array(natural range <>) of std_logic_vector(7 downto 0);
signal mem : memory_arr_t(0 to 63); -- Memory array
signal addr_s : integer range 0 to 63; -- Memory access address
begin -- architecture RTL
addr_s <= to_integer(unsigned(address));
memory_proc : process is
begin
wait until rising_edge(clk);
if write_enable = '1' then
mem(addr_s) <= write_data;
end if;
if read_enable = '1' then
read_data <= mem(addr_s);
end if;
end process memory_proc;
end architecture RTL;

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rtl/mem/flacdec_byte_fifo.vhd
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@ -1,143 +0,0 @@
-------------------------------------------------------------------------------
-- Title : FIFO for 8 bit data
-- Project : VHDL FLAC Decoder
-------------------------------------------------------------------------------
-- File : flacdec_byte_fifo.vhd
-- Author : Mario Huettel <mario.huettel@linux.com>
-- Company :
-- Created : 2023-10-05
-- Last update: 2023-10-05
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This is a generic FIFO implementation for 8 bit Data. This
-- implementation should be able to map to a dual ported BRAM in an FPGA. If an
-- ASIC Design is used, decide weather to use a RAM instance or let the
-- synthesis generate a FIFO out of Flip Flops.
-- The FIFO is 64 bytes large.
-------------------------------------------------------------------------------
-- Copyright (c) 2023 Mario Huettel
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity flacdec_byte_fifo is
port (
clk : in std_logic; -- Clock
rst_n : in std_logic; -- async. low-active reset
data_in : in std_logic_vector(7 downto 0);
data_in_wstrb : in std_logic; -- Write strobe to push data into the FIFO
data_out : out std_logic_vector(7 downto 0); -- Output data. 1 cycle delayed after read strobe.
data_rstrb : in std_logic;
fifo_full : out std_logic; -- FIFO is full
fifo_empty : out std_logic; -- FIFO is empty
fifo_32_free : out std_logic); -- FIFO has at least 32 bytes free
end entity flacdec_byte_fifo;
architecture RTL of flacdec_byte_fifo is
type fifo_mem_t is array(natural range <>) of std_logic_vector(data_in'range);
signal mem : fifo_mem_t(0 to 63);
signal read_ptr : unsigned(6 downto 0);
signal write_ptr : unsigned(6 downto 0);
signal write_strb_s : std_logic;
signal read_strb_s : std_logic;
signal write_addr : unsigned(5 downto 0);
signal read_addr : unsigned(5 downto 0);
signal fifo_fill_level : integer range 0 to 64;
signal wrapped_around : std_logic;
signal fifo_full_s : std_logic;
signal fifo_empty_s : std_logic;
begin -- architecture RTL
fifo_full <= fifo_full_s;
fifo_empty <= fifo_empty_s;
--------------------------------------------------------------------------
-- FIFO memory implementation
--------------------------------------------------------------------------
-- FIFO memory process. Should allow BRAM infer.
fifo_mem_proc : process is
begin
wait until rising_edge(clk);
if write_strb_s = '1' then
mem(to_integer(write_addr)) <= data_in;
end if;
if read_strb_s = '1' then
data_out <= mem(to_integer(read_addr));
end if;
end process fifo_mem_proc;
--------------------------------------------------------------------------
-- FIFO fill level and address logic
--------------------------------------------------------------------------
-- Addresses to memory are the pointers except for the MSB, which is used
-- for wrap around detection
read_addr <= read_ptr(read_ptr'high - 1 downto read_ptr'low);
write_addr <= write_ptr(write_ptr'high - 1 downto write_ptr'low);
wrapped_around <= '1' when read_ptr(read_ptr'high) /= write_ptr(write_ptr'high) else '0';
fill_level_proc : process(wrapped_around, read_addr, write_addr) is
begin
fifo_fill_level <= 0;
if wrapped_around = '0' then
fifo_fill_level <= to_integer(write_addr - read_addr);
else
fifo_fill_level <= to_integer(64 - read_addr + write_addr);
end if;
end process fill_level_proc;
fifo_full_s <= '1' when read_addr = write_addr and wrapped_around = '1' else '0';
fifo_empty_s <= '1' when read_addr = write_addr and wrapped_around = '0' else '0';
fifo_32_free <= '1' when fifo_fill_level >= 32 else '0';
---------------------------------------------------------------------------
-- FIFO write pointer
---------------------------------------------------------------------------
write_strb_s <= data_in_wstrb and (not fifo_full_s);
write_ptr_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
write_ptr <= (others => '0');
elsif rising_edge(clk) then
if write_strb_s = '1' then
-- Wrap around expected
write_ptr <= write_ptr + 1;
end if;
end if;
end process write_ptr_proc;
---------------------------------------------------------------------------
-- FIFO read pointer
---------------------------------------------------------------------------
read_strb_s <= data_rstrb and (not fifo_empty_s);
read_ptr_proc : process(clk, rst_n) is
begin
if rst_n = '0' then
read_ptr <= (others => '0');
elsif rising_edge(clk) then
if read_strb_s = '1' then
-- Wrap around expected
read_ptr <= read_ptr + 1;
end if;
end if;
end process read_ptr_proc;
end architecture RTL;

4
verif/.gitignore vendored
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@ -9,6 +9,10 @@ __pycache__/
# C extensions # C extensions
*.so *.so
*.o
# Simulation waveforms
*.ghw
# Distribution / packaging # Distribution / packaging
.Python .Python

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verif/input_fifo_tb/poetry.lock generated Normal file
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python-versions = "^3.11"
content-hash = "6891ff82be122556d540c217ca1e66b41cf7af93b77485f951064028e5edadcb"

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[tool.poetry]
name = "input-fifo-tb"
version = "0.1.0"
description = ""
authors = ["Mario Huettel <mario.huettel@linux.com>"]
readme = "README.md"
[tool.poetry.dependencies]
python = "^3.11"
cocotb = "^1.8.1"
cocotbext-axi = "^0.1.24"
cocotb-coverage = "^1.1.0"
[build-system]
requires = ["poetry-core"]
build-backend = "poetry.core.masonry.api"

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<testsuites name="results">
<testsuite name="all" package="all">
<property name="random_seed" value="1696789703" />
<testcase name="test_fifo_fill" classname="tb.tests" file="/home/mhu/projects/fpga/vhdl-flac-decode/verif/input_fifo_tb/tb/tests.py" lineno="26" time="0.018865585327148438" sim_time_ns="2750.000001" ratio_time="145768.07203763907" />
<testcase name="stress_test_001" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.009937286376953125" sim_time_ns="2070.000001" ratio_time="208306.36478393243" />
<testcase name="stress_test_002" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.013479232788085938" sim_time_ns="2070.0000010000003" ratio_time="153569.57132082753" />
<testcase name="stress_test_003" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.01352071762084961" sim_time_ns="2070.0000009999994" ratio_time="153098.38272252338" />
<testcase name="stress_test_004" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.01389002799987793" sim_time_ns="2270.0000010000003" ratio_time="163426.59647769967" />
<testcase name="stress_test_005" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.017490386962890625" sim_time_ns="2390.0000010000003" ratio_time="136646.4907878177" />
<testcase name="stress_test_006" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.01611948013305664" sim_time_ns="2390.0000010000003" ratio_time="148267.80896604504" />
<testcase name="stress_test_007" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.013995170593261719" sim_time_ns="2070.0000009999985" ratio_time="147908.16497775636" />
<testcase name="stress_test_008" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.020600318908691406" sim_time_ns="2070.0000010000003" ratio_time="100483.88135033454" />
<testcase name="stress_test_009" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.011068105697631836" sim_time_ns="2070.0000010000003" ratio_time="187023.87360132489" />
<testcase name="stress_test_010" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.010287284851074219" sim_time_ns="2190.0000010000003" ratio_time="212884.16066084884" />
<testcase name="stress_test_011" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.01676630973815918" sim_time_ns="2610.0000010000003" ratio_time="155669.31792150938" />
<testcase name="stress_test_012" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.014882326126098633" sim_time_ns="2210.0000010000003" ratio_time="148498.29134737197" />
<testcase name="stress_test_013" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.018981456756591797" sim_time_ns="3110.0000010000003" ratio_time="163844.11591170277" />
<testcase name="stress_test_014" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.01958465576171875" sim_time_ns="2990.0000009999967" ratio_time="152670.54153917864" />
<testcase name="stress_test_015" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.01961994171142578" sim_time_ns="2990.0000010000003" ratio_time="152395.96758122667" />
<testcase name="stress_test_016" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.010677099227905273" sim_time_ns="2230.0000010000003" ratio_time="208858.22575964776" />
<testcase name="stress_test_017" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.015899181365966797" sim_time_ns="2430.0000010000003" ratio_time="152838.057826145" />
<testcase name="stress_test_018" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="0.015126705169677734" sim_time_ns="2270.0000010000003" ratio_time="150065.72651064378" />
<testcase name="stress_test_019" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="13.715387344360352" sim_time_ns="1229370.000001" ratio_time="89634.36242334827" />
<testcase name="stress_test_020" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="51.89472937583923" sim_time_ns="7365570.000000999" ratio_time="141932.9108869042" />
<testcase name="stress_test_021" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="17.472015380859375" sim_time_ns="1755330.0000010002" ratio_time="100465.22749310119" />
<testcase name="stress_test_022" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="76.48135256767273" sim_time_ns="12274790.000001" ratio_time="160493.8927974625" />
<testcase name="stress_test_023" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="83.74765825271606" sim_time_ns="12274790.000000998" ratio_time="146568.75494907235" />
<testcase name="stress_test_024" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="83.08736419677734" sim_time_ns="12274790.000000998" ratio_time="147733.53467959803" />
<testcase name="stress_test_025" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="15.489974975585938" sim_time_ns="1418150.0000010058" ratio_time="91552.76249549664" />
<testcase name="stress_test_026" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="45.35286903381348" sim_time_ns="7365590.000000998" ratio_time="162406.2635267788" />
<testcase name="stress_test_027" classname="tb.tests" file="/home/mhu/.cache/pypoetry/virtualenvs/input-fifo-tb-X8E_jJha-py3.11/lib/python3.11/site-packages/cocotb/regression.py" lineno="731" time="19.35894203186035" sim_time_ns="1755330.0000009984" ratio_time="90672.82690924588" />
</testsuite>
</testsuites>

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#!/bin/bash
SOURCE=${BASH_SOURCE[0]}
while [ -L "$SOURCE" ]; do # resolve $SOURCE until the file is no longer a symlink
DIR=$( cd -P "$( dirname "$SOURCE" )" >/dev/null 2>&1 && pwd )
SOURCE=$(readlink "$SOURCE")
[[ $SOURCE != /* ]] && SOURCE=$DIR/$SOURCE # if $SOURCE was a relative symlink, we need to resolve it relative to the path where the symlink file was located
done
SCRIPT_DIR=$( cd -P "$( dirname "$SOURCE" )" >/dev/null 2>&1 && pwd )
projdir=`readlink -f -n "$SCRIPT_DIR/../../"`
workdir=`mktemp -d`
echo "Using tempdir: $workdir"
toplevel="flacdec_input_fifo"
filelist=("rtl/flacdec_double_mem_fifo.vhd" "rtl/mem/flacdec_64x08_memory.vhd" "rtl/flacdec_input_fifo.vhd")
cd "$SCRIPT_DIR"
for file in ${filelist[@]}; do
echo "Importing $file"
ghdl -i --workdir="$workdir" "$projdir/$file"
done
echo "Building design..."
ghdl -m --workdir="$workdir" $toplevel
export LIBPYTHON_LOC=`cocotb-config --libpython`
export MODULE=tb.tests
ghdl -r --workdir="$workdir" "$toplevel" --vpi=$(cocotb-config --lib-name-path vpi ghdl)
cd "$projdir"
rm -rf "$rundir"

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verif/input_fifo_tb/tb/__init__.py Normal file
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import cocotb
from cocotb.triggers import RisingEdge, FallingEdge, Edge
from cocotb.triggers import Timer
from cocotbext.axi import (AxiStreamBus, AxiStreamSource, AxiStreamSink, AxiStreamMonitor, AxiStreamFrame)
from random import randint, randrange
from cocotb.regression import TestFactory
from itertools import cycle
async def reset_target(dut):
dut.rst_n.value = 0
dut.out_tready.value = 0
dut.flush_output.value = 0
dut.clear.value = 0
await Timer(10, units='ns')
await RisingEdge(dut.clk)
dut.rst_n.value = 1
async def clock_driver(dut):
while True:
dut.clk.value = 0
await Timer(10, units='ns')
dut.clk.value = 1
await Timer(10, units='ns')
@cocotb.test()
async def test_fifo_fill(dut):
axi_in = AxiStreamSource(AxiStreamBus.from_prefix(dut, 'in'), dut.clk, dut.rst_n, reset_active_level=False)
cocotb.start_soon(clock_driver(dut))
await reset_target(dut)
frame = bytearray([randint(0, 2**8-1) for _ in range(128+2)])
await axi_in.send(frame)
await axi_in.wait()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
assert dut.in_tready.value == 1, 'FIFO full + pipeline full'
assert dut.full.value == 1, 'FIFO full?'
await axi_in.send(bytearray([randint(0, 255)]))
await axi_in.wait()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
assert dut.in_tready.value == 0, 'FIFO full + pipeline full'
assert dut.full.value == 1, 'FIFO full'
assert dut.empty.value == 0, 'FIFO empty'
async def stress_test(dut, tx_pause=None, rx_pause=None, count=512):
axi_in = AxiStreamSource(AxiStreamBus.from_prefix(dut, 'in'), dut.clk, dut.rst_n, reset_active_level=False)
axi_out = AxiStreamSink(AxiStreamBus.from_prefix(dut, "out"), dut.clk, dut.rst_n, reset_active_level=False)
cocotb.start_soon(clock_driver(dut))
await reset_target(dut)
if tx_pause:
axi_in.set_pause_generator(tx_pause)
if rx_pause:
axi_out.set_pause_generator(rx_pause)
frame = bytearray([randint(0, 255) for _ in range(count)])
await axi_in.send(frame)
await axi_in.wait()
for _ in range(count*100):
await RisingEdge(dut.clk)
if dut.flacdec_double_mem_fifo_1.fill_level.value == 0:
break
else:
assert False, 'Timeout'
for _ in range(100):
await RisingEdge(dut.clk)
rx_data = await axi_out.read(axi_out.count())
assert len(rx_data) == len(frame), 'RX TX data count mismatch'
for tx, rx in zip(frame, rx_data):
assert tx == rx, 'TX, RX data mismatch'
stress_test_fac = TestFactory(stress_test)
stress_test_fac.add_option('count', [1, 5, randint(1000, 2**16)])
def generate_random_wait_seq(percent=50, length=20):
seq = [1 if randint(0, 100) >= percent else 0 for _ in range(length)]
return seq
stress_test_fac.add_option('tx_pause', [None, cycle(generate_random_wait_seq(10, 30)), cycle(generate_random_wait_seq(80, 30))])
stress_test_fac.add_option('rx_pause', [None, cycle(generate_random_wait_seq(10, 30)), cycle(generate_random_wait_seq(80, 30))])
stress_test_fac.generate_tests()