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Mario Hüttel
mhu
1 Followers
·
1 Following
Germany
https://shimatta.de
Joined on
2016-08-02
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Repositories
37
Projects
Packages
Public Activity
Starred Repositories
2
mhu
pushed to
master
at
pcb/shimatta-pcb-libs
2017-01-10 14:02:35 +01:00
1b0f13bd16
added 3d model for coil
mhu
pushed tag
V1.2
to
pcb/dvi-fpga
2017-01-08 22:38:32 +01:00
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-08 21:58:03 +01:00
41e33910d6
added vias in power supply for TFP401
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-08 21:43:30 +01:00
9a04fc70b8
improved layout
mhu
pushed to
master
at
pcb/shimatta-pcb-libs
2017-01-08 21:35:08 +01:00
703d820b95
added coil footprint
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-08 21:29:35 +01:00
202c925e6e
redone switching regulator
mhu
pushed tag
V1.1
to
pcb/dvi-fpga
2017-01-08 14:01:07 +01:00
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-08 13:59:54 +01:00
65db531300
removed track
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-08 13:57:12 +01:00
4d9c0971b2
added version number to pcb
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-08 13:56:07 +01:00
8561e71ad7
remove 5V output, increased input voltage to 9V+ because regulator is not stable with 5V in
mhu
pushed tag
V1.0
to
pcb/dvi-fpga
2017-01-07 00:25:42 +01:00
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-07 00:19:00 +01:00
f45251d2d0
added cap in PVDD/OVDD of TFP401
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-06 18:11:23 +01:00
181ea5802a
moved input cap to bottom layer, improve routing of +2V5
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-06 16:28:03 +01:00
7e5fce5379
moved footprints, checked silkscreen positions, reinforced some power tracks
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-05 23:20:17 +01:00
23596b6827
improved layout
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-05 21:39:58 +01:00
a163647422
exchanged ceramic caps with tantal
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-05 20:05:34 +01:00
ad263474a2
fixed GND connection of cap for regulator
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-04 21:31:08 +01:00
ab8a7ae856
fixed routing, moved caps to bottom layer, added caps for 5V rail
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-04 03:06:09 +01:00
716c1b88e5
fixed cap in VIO for FPGA, added project/my name and date
mhu
pushed to
master
at
pcb/dvi-fpga
2017-01-03 15:27:06 +01:00
9b88a8374f
fixed unconnected pin
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