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Add vias to erath net

This commit is contained in:
Mario Hüttel 2020-02-18 20:45:31 +01:00
parent c35760c5dd
commit 6f93679416
1 changed files with 4 additions and 28 deletions
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reflow-oven-control-pcb.kicad_pcb
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@ -6676,8 +6676,8 @@
(gr_line (start 98 113) (end 98 13) (layer Edge.Cuts) (width 0.05))
(gr_line (start 18 113) (end 98 113) (layer Edge.Cuts) (width 0.05))
(via (at 23.5 112) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 0))
(via (at 74.75 112) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 0))
(via (at 23.5 112) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(via (at 74.75 112) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 97.25 96.75) (end 91.5 102.5) (width 0.3) (layer B.Cu) (net 1) (status 20))
(segment (start 97 88) (end 97.25 87.75) (width 0.3) (layer B.Cu) (net 1))
(segment (start 22.5 19.1) (end 22.5 16.5) (width 0.3) (layer F.Cu) (net 1))
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