pcb/reflow-oven-control-pcb
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Make 230V port wider and add eeprom for config

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This commit is contained in:
Mario Hüttel 2020-04-14 21:23:59 +02:00
parent e18bc9558c
commit ff81a12896
5 changed files with 3427 additions and 3003 deletions
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26
reflow-oven-control-pcb-cache.lib
View File

@ -635,6 +635,32 @@ X 1 1 0 -100 100 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# Memory_EEPROM_25LCxxx
#
DEF Memory_EEPROM_25LCxxx U 0 20 Y Y 1 F N
F0 "U" -300 250 50 H V C CNN
F1 "Memory_EEPROM_25LCxxx" 100 -250 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS BR25Sxxx CAT250xxx AT25xxx
$FPLIST
DIP*W7.62mm*
SOIC*3.9x4.9mm*
TSSOP*4.4x3mm*P0.65mm*
$ENDFPLIST
DRAW
S -300 200 300 -200 1 1 10 f
X ~CS 1 -400 -100 100 R 50 50 1 1 I
X MISO 2 400 -100 100 L 50 50 1 1 T
X ~WP 3 -400 100 100 R 50 50 1 1 I
X GND 4 0 -300 100 U 50 50 1 1 W
X MOSI 5 400 0 100 L 50 50 1 1 I
X SCK 6 400 100 100 L 50 50 1 1 I
X ~HOLD 7 -400 0 100 R 50 50 1 1 I
X VCC 8 0 300 100 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# Power_Protection_USBLC6-2SC6
#
DEF Power_Protection_USBLC6-2SC6 U 0 0 Y Y 1 F N

6249
reflow-oven-control-pcb.kicad_pcb
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File diff suppressed because it is too large Load Diff

22
reflow-oven-control-pcb.pro
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@ -1,4 +1,4 @@
update=Fri 03 Jan 2020 08:43:13 PM CET
update=Tue 18 Feb 2020 09:42:41 PM CET
version=1
last_client=kicad
[general]
@ -12,16 +12,6 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
@ -264,3 +254,13 @@ uViaDrill=0.1
dPairWidth=0.21
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

2
reflow-oven-control-pcb.sch
View File

@ -19,7 +19,7 @@ U 1 1 5D6DCF6A
P 1100 1000
F 0 "J101" H 1018 675 50 0000 C CNN
F 1 "230VAC IN" H 1018 766 50 0000 C CNN
F 2 "TerminalBlock:TerminalBlock_Altech_AK300-3_P5.00mm" H 1100 1000 50 0001 C CNN
F 2 "TerminalBlock_RND:TerminalBlock_RND_205-00068_1x03_P7.50mm_Horizontal" H 1100 1000 50 0001 C CNN
F 3 "~" H 1100 1000 50 0001 C CNN
1 1100 1000
-1 0 0 1

131
stm.sch
View File

@ -17,8 +17,8 @@ $Comp
L MCU_ST_STM32F4:STM32F407VETx U202
U 1 1 5D78060E
P 5650 3850
F 0 "U202" H 5650 961 50 0000 C CNN
F 1 "STM32F407VETx" H 5650 870 50 0000 C CNN
F 0 "U202" H 5650 3850 50 0000 C CNN
F 1 "STM32F407VETx" H 5650 3750 50 0000 C CNN
F 2 "Package_QFP:LQFP-100_14x14mm_P0.5mm" H 4950 1250 50 0001 R CNN
F 3 "http://www.st.com/st-web-ui/static/active/en/resource/technical/document/datasheet/DM00037051.pdf" H 5650 3850 50 0001 C CNN
1 5650 3850
@ -724,8 +724,8 @@ $Comp
L 74xx:74HCT244 U201
U 1 1 5D90FF0A
P 3450 6150
F 0 "U201" H 3450 7131 50 0000 C CNN
F 1 "74HCT244" H 3450 7040 50 0000 C CNN
F 0 "U201" H 4000 5750 50 0000 C CNN
F 1 "74HCT244" H 4000 5650 50 0000 C CNN
F 2 "Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm" H 3450 6150 50 0001 C CNN
F 3 "https://assets.nexperia.com/documents/data-sheet/74HC_HCT244.pdf" H 3450 6150 50 0001 C CNN
1 3450 6150
@ -1685,4 +1685,127 @@ Wire Wire Line
800 5850 1300 5850
Wire Wire Line
1300 5850 1300 6050
$Comp
L Memory_EEPROM:25LCxxx U203
U 1 1 5E9C446B
P 8000 4500
F 0 "U203" H 8000 4981 50 0000 C CNN
F 1 "25LCxxx" H 8000 4890 50 0000 C CNN
F 2 "Package_SO:SO-8_5.3x6.2mm_P1.27mm" H 8000 4500 50 0001 C CNN
F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/21832H.pdf" H 8000 4500 50 0001 C CNN
1 8000 4500
1 0 0 -1
$EndComp
$Comp
L power:+3V3 #PWR0140
U 1 1 5E9C6971
P 8000 3950
F 0 "#PWR0140" H 8000 3800 50 0001 C CNN
F 1 "+3V3" H 8015 4123 50 0000 C CNN
F 2 "" H 8000 3950 50 0001 C CNN
F 3 "" H 8000 3950 50 0001 C CNN
1 8000 3950
1 0 0 -1
$EndComp
Wire Wire Line
8000 3950 8000 4100
Wire Wire Line
8650 4400 8650 4900
Wire Wire Line
8650 4900 7250 4900
Wire Wire Line
8400 4400 8650 4400
Text Label 7600 4900 0 50 ~ 0
SPI2_SCK
Wire Wire Line
6550 4450 7250 4450
Wire Wire Line
7250 4450 7250 4900
Wire Wire Line
6550 4550 7100 4550
Wire Wire Line
7100 4550 7100 5000
Wire Wire Line
7100 5000 8500 5000
Wire Wire Line
8500 5000 8500 4600
Wire Wire Line
8500 4600 8400 4600
Wire Wire Line
7600 4400 7500 4400
Wire Wire Line
7500 4400 7500 4100
Wire Wire Line
7500 4100 8000 4100
Connection ~ 8000 4100
Wire Wire Line
8000 4100 8000 4200
Wire Wire Line
7600 4500 7500 4500
Wire Wire Line
7500 4500 7500 4400
Connection ~ 7500 4400
Wire Wire Line
6550 4650 7000 4650
Wire Wire Line
7000 4650 7000 5100
Wire Wire Line
7000 5100 8750 5100
Wire Wire Line
8750 5100 8750 4500
Wire Wire Line
8750 4500 8400 4500
Text Label 7600 5100 0 50 ~ 0
SPI2_MOSI
Text Label 7600 5000 0 50 ~ 0
SPI2_MISO
Wire Wire Line
8000 4800 8000 5200
$Comp
L power:GND #PWR0141
U 1 1 5EA90D48
P 8000 5200
F 0 "#PWR0141" H 8000 4950 50 0001 C CNN
F 1 "GND" H 8005 5027 50 0000 C CNN
F 2 "" H 8000 5200 50 0001 C CNN
F 3 "" H 8000 5200 50 0001 C CNN
1 8000 5200
1 0 0 -1
$EndComp
$Comp
L Device:C C220
U 1 1 5EAAB237
P 8950 4350
F 0 "C220" H 9065 4396 50 0000 L CNN
F 1 "100n" H 9065 4305 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 8988 4200 50 0001 C CNN
F 3 "~" H 8950 4350 50 0001 C CNN
1 8950 4350
1 0 0 -1
$EndComp
Wire Wire Line
8950 4200 8950 4100
Wire Wire Line
8000 4100 8950 4100
$Comp
L power:GND #PWR0142
U 1 1 5EAC550F
P 8950 4650
F 0 "#PWR0142" H 8950 4400 50 0001 C CNN
F 1 "GND" H 8955 4477 50 0000 C CNN
F 2 "" H 8950 4650 50 0001 C CNN
F 3 "" H 8950 4650 50 0001 C CNN
1 8950 4650
1 0 0 -1
$EndComp
Wire Wire Line
8950 4650 8950 4500
Wire Wire Line
7600 4600 7350 4600
Wire Wire Line
7350 4600 7350 4350
Wire Wire Line
7350 4350 6550 4350
Text Label 6700 4350 0 50 ~ 0
~CS~_EEPROM
$EndSCHEMATC