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v1.0

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• 93ae71bcbc Add programming files for FTDI EEPROM master Mario Hüttel 2021-06-20 12:37:04 +0200
• 5dba0f8e2d Perform final DRC and generate gerbers for v1.0 v1.0 Mario Hüttel 2021-05-25 22:58:09 +0200
• 4d5ea12e7e Length match RS485 (Yeah... I know its's not necessary. But it looks cool, right?) Mario Hüttel 2021-05-24 02:38:08 +0200
• 1387a0985b Fix silkscreen Mario Hüttel 2021-05-22 22:21:55 +0200
• 0523f0c751 Finalize layout Mario Hüttel 2021-05-22 22:12:36 +0200
• 0f977f2eaa Change switch Mario Hüttel 2021-05-22 22:03:39 +0200
• 34d2778601 Fix #6: Remove unnecessary caps Mario Hüttel 2021-05-22 21:46:37 +0200
• 7bda3e7e27 Fix #3: Add Ployfuse with 500 mA to 5V supply Mario Hüttel 2021-05-22 21:40:42 +0200
• 1cd1b5138b Fix #7 Mario Hüttel 2021-05-22 21:23:03 +0200
• b86ef7a4cc slighly move a trace to make via fully enclosed in GND plane Mario Hüttel 2021-05-16 21:19:38 +0200
• e8315448dd Add possibility to supply target from JTAG input port Pin 19 (JLink can supply 5V on that pin) Mario Hüttel 2021-05-16 21:18:05 +0200
• 939c3683e8 Rename nets and round PCB corners Mario Hüttel 2021-05-16 17:51:57 +0200
• 2f1fa13ae1 Add labeling for git repository Mario Hüttel 2021-05-16 17:38:34 +0200
• c453f96bdb First draft. Correct labeling still missing Mario Hüttel 2021-05-16 17:36:18 +0200