added address and mask arrays to aw rounter. aw router started
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@ -11,13 +11,56 @@ entity axi3intercon_aw_router is
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rst : in std_logic;
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masters_out : in axi_aw_masters_out_t(0 to MASTER_COUNT - 1);
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masters_in : out axi_aw_masters_in_t(0 to MASTER_COUNT - 1);
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slaves_out : in axi_aw_slaves_out_t(0 to SLAVE_COUNT - 1);
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slaves_in : out axi_aw_slaves_in_t(0 to SLAVE_COUNT - 1);
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write_locks : out write_locks_t(0 to MASTER_COUNT - 1);
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write_releases : in write_release_t
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slaves_out : in axi_aw_slaves_out_t(0 to SLAVE_COUNT);
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slaves_in : out axi_aw_slaves_in_t(0 to SLAVE_COUNT);
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write_locks : out write_locks_t(0 to MASTER_COUNT - 1); -- write_* signals come/go from/to the write router.
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write_releases : in write_release_t;
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address_array : in axi_slave_addresses_t(0 to SLAVE_COUNT - 1);
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mask_array : in axi_slave_addresses_t(0 to SLAVE_COUNT - 1)
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);
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end entity axi3intercon_aw_router;
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architecture RTL of axi3intercon_aw_router is
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alias clk is aclk;
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type aw_state_t is (READY, ACTIVE, BLK);
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type aw_states_t is array (0 to MASTER_COUNT - 1) of aw_state_t;
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signal aw_states : aw_states_t;
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begin
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aw_router : process(clk, rst) is
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variable slave_block : std_logic_vector(0 to SLAVE_COUNT - 1) := (others => '0');
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variable slave_idx : integer range 0 to SLAVE_COUNT := SLAVE_COUNT; -- 1 more slave than connected for handling bad requests.
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procedure calculate_slave(address : in std_logic_vector(ADDRESS_BITS - 1 downto 0)) is
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begin
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slave_idx := SLAVE_COUNT;
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for i in 0 to SLAVE_COUNT - 1 loop
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if (address and mask_array(i)) = address_array(i) then
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slave_idx := i;
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end if;
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end loop;
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end procedure calculate_slave;
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begin
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if rst = '1' then
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for i in 0 to MASTER_COUNT - 1 loop
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aw_states(i) <= READY;
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end loop;
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slave_block := (others => '0');
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elsif rising_edge(clk) then
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for i in MASTER_COUNT - 1 downto 0 loop -- Loop for every master
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case aw_states(i) is
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when READY =>
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if masters_out(i).awvalid = '1' then
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calculate_slave(masters_out(i).awaddr);
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-- TODO: Write router itself
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-- TODO: lock output
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end if;
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when others => null;
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end case;
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end loop;
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end if;
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end process aw_router;
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end architecture RTL;
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@ -11,7 +11,7 @@ package axi_aw_router_pkg is
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type write_lock_t is record
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locked : std_logic;
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slave_idx : integer range 0 to SLAVE_COUNT - 1;
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slave_idx : integer range 0 to SLAVE_COUNT;
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end record write_lock_t;
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type write_locks_t is array (natural range <>) of write_lock_t;
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@ -17,13 +17,16 @@ entity axi3intercon is
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end entity axi3intercon;
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architecture RTL of axi3intercon is
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signal address_array : axi_slave_addresses_t(0 to SLAVE_COUNT - 1);
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signal mask_array : axi_slave_addresses_t(0 to SLAVE_COUNT - 1);
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signal rst : std_logic;
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signal write_locks : write_locks_t(0 to MASTER_COUNT - 1);
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signal write_releases : write_release_t;
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signal aw_masters_out : axi_aw_masters_out_t(0 to MASTER_COUNT - 1);
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signal aw_masters_in : axi_aw_masters_in_t(0 to MASTER_COUNT - 1);
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signal aw_slaves_out : axi_aw_slaves_out_t(0 to SLAVE_COUNT - 1);
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signal aw_slaves_in : axi_aw_slaves_in_t(0 to SLAVE_COUNT - 1);
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signal aw_slaves_out : axi_aw_slaves_out_t(0 to SLAVE_COUNT);
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signal aw_slaves_in : axi_aw_slaves_in_t(0 to SLAVE_COUNT);
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begin
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reset_sync : process(aclk, aresetn) is
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begin
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@ -43,7 +46,9 @@ begin
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slaves_out => aw_slaves_out,
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slaves_in => aw_slaves_in,
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write_locks => write_locks,
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write_releases => write_releases
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write_releases => write_releases,
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address_array => address_array,
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mask_array => mask_array
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);
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aw_master_connect : for i in 0 to MASTER_COUNT - 1 generate
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@ -210,13 +210,15 @@ package axi3intercon_pkg is
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b : slave_b_out_t;
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end record axi_slave_out_t;
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-- Array definitions
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-- Connection array definitions
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type axi_masters_in_t is array (natural range <>) of axi_master_in_t;
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type axi_masters_out_t is array (natural range <>) of axi_master_out_t;
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type axi_slaves_in_t is array (natural range <>) of axi_slave_in_t;
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type axi_slaves_out_t is array (natural range <>) of axi_slave_out_t;
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-- Address translation mapping
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type axi_slave_addresses_t is array (natural range <>) of std_logic_vector(ADDRESS_BITS - 1 downto 0);
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end package axi3intercon_pkg;
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-- package body axi3intercon_pkg is
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