fpga/axi3-interconnect
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remove package body, changed aliases to subtypes

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This commit is contained in:
Mario Hüttel 2016-08-20 18:08:38 +02:00
parent c35444e55a
commit 772ccc0da8
2 changed files with 6 additions and 6 deletions
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2
.library_mapping.xml
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@ -1,6 +1,6 @@
<?xml version="1.0" encoding="UTF-8"?>
<com.sigasi.hdt.shared.librarymapping.model:LibraryMappings xmlns:com.sigasi.hdt.shared.librarymapping.model="com.sigasi.hdt.vhdl.scoping.librarymapping" Version="2">
<Mappings Location="src" Library="axi3intercon"/>
<Mappings Location="src" Library="axi3interconnect"/>
<Mappings Location="Common Libraries/IEEE" Library="ieee"/>
<Mappings Location="Common Libraries" Library="not mapped"/>
<Mappings Location="Common Libraries/STD" Library="std"/>

10
src/axi3-interconnect_pkg.vhd
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@ -44,7 +44,7 @@ package axi3intercon_pkg is
awvalid : std_logic; -- Data valid
end record slave_aw_in;
alias slave_aw_out is master_aw_in;
subtype slave_aw_out is master_aw_in;
-- type decalatations for AR cahnnel
type master_ar_out is record
@ -75,7 +75,7 @@ package axi3intercon_pkg is
arvalid : std_logic; -- Data valid
end record slave_ar_in;
alias slave_ar_out is master_ar_in;
subtype slave_ar_out is master_ar_in;
-- type decalarations for W channel
type master_w_out is record
@ -100,8 +100,8 @@ package axi3intercon_pkg is
wready : std_logic;
end record master_w_in;
alias slave_w_out is master_w_in;
subtype slave_w_out is master_w_in;
end package axi3intercon_pkg;
package body axi3intercon_pkg is
end package body axi3intercon_pkg;
-- package body axi3intercon_pkg is
-- end package body axi3intercon_pkg;