started default slave that is accessed on decerr, write read error

src/axi3-interconnect-decerr.vhd

@@ -0,0 +1,64 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.axi3intercon_pkg.all;
+
+entity filename is
+	port(
+		clk       : in  std_logic;
+		rst       : in  std_logic;
+		slave_in  : in  axi_slave_in_t;
+		slave_out : out axi_slave_out_t
+	);
+end entity filename;
+
+architecture RTL of filename is
+	type r_state_t is (R_READY, R_ERROR);
+	signal r_state : r_state_t;
+	signal r_len   : unsigned(7 downto 0);
+begin
+	read_error : process(clk, rst) is
+	begin
+		if rst = '1' then
+			slave_out.ar.arready <= '0';
+			slave_out.r.rdata    <= (others => '0');
+			slave_out.r.rid      <= (others => '0');
+			slave_out.r.rlast    <= '0';
+			slave_out.r.rresp    <= (others => '0');
+			slave_out.r.ruser    <= (others => '0');
+			slave_out.r.rvalid   <= '0';
+		elsif rising_edge(clk) then
+			case r_state is
+				when R_READY =>
+					slave_out.r.rlast <= '0';
+					if slave_in.ar.arvalid = '1' then
+						slave_out.ar.arready <= '1';
+						r_state              <= R_ERROR;
+						slave_out.r.rid      <= slave_in.ar.arid;
+						slave_out.r.rresp    <= AXI_RESP_DECERR;
+						slave_out.r.rvalid   <= '1';
+						if unsigned(slave_in.ar.arlen) = 1 then
+							slave_out.r.rlast <= '1';
+						else
+							slave_out.r.rlast <= '0';
+						end if;
+						r_len <= unsigned(slave_in.ar.arlen);
+					end if;
+				when R_ERROR =>
+					slave_out.ar.arready <= '0';
+					slave_out.r.rvalid   <= '1';
+					if slave_in.r.rready = '1' then
+						r_len <= r_len - 1;
+						if r_len = 2 then
+							slave_out.r.rlast <= '1';
+						end if;
+						if r_len = to_unsigned(1, r_len'length) then
+							r_state            <= R_READY;
+							slave_out.r.rvalid <= '0';
+						end if;
+					end if;
+			end case;
+		end if;
+	end process read_error;
+
+end architecture RTL;