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fpga
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axi3-interconnect
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8ebb16e4d8e07f0bfcc7337491de0cd0c64dbf8e
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Mario Hüttel
8ebb16e4d8
started default slave that is accessed on decerr, write read error
2016-08-23 18:43:34 +02:00
.settings
started type definitions
2016-08-20 14:43:06 +02:00
src
started default slave that is accessed on decerr, write read error
2016-08-23 18:43:34 +02:00
.gitignore
started type definitions
2016-08-20 14:43:06 +02:00
.library_mapping.xml
remove package body, changed aliases to subtypes
2016-08-20 18:08:38 +02:00
.project
started type definitions
2016-08-20 14:43:06 +02:00
Description
AXI3 crossbar interconnect
64
KiB
Languages
VHDL
99.3%
Shell
0.7%