fpga/axi3-interconnect
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fixed aw router to fut VHDL93

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This commit is contained in:
Mario Hüttel 2016-08-21 20:54:02 +02:00
parent d272ed687b
commit c660af5df0
1 changed files with 10 additions and 5 deletions
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13
src/axi3-interconnect-aw-router.vhd
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@ -26,9 +26,14 @@ architecture RTL of axi3intercon_aw_router is
type aw_states_t is array (0 to MASTER_COUNT - 1) of aw_state_t; type aw_states_t is array (0 to MASTER_COUNT - 1) of aw_state_t;
signal aw_states : aw_states_t; signal aw_states : aw_states_t;
signal write_locks_s : write_locks_t(0 to MASTER_COUNT - 1); signal write_locks_s : write_locks_t(0 to MASTER_COUNT - 1);
signal awready_s : std_logic_vector(0 to MASTER_COUNT - 1);
begin begin
write_locks <= write_locks_s; write_locks <= write_locks_s;
awready_gen : for i in 0 to MASTER_COUNT - 1 generate
masters_in(i).awready <= awready_s(i);
end generate awready_gen;
aw_router : process(clk, rst) is aw_router : process(clk, rst) is
variable slave_idx : integer range 0 to SLAVE_COUNT := SLAVE_COUNT; -- 1 more slave than connected for handling bad requests. variable slave_idx : integer range 0 to SLAVE_COUNT := SLAVE_COUNT; -- 1 more slave than connected for handling bad requests.
variable slave_in_use : std_logic_vector(0 to SLAVE_COUNT); variable slave_in_use : std_logic_vector(0 to SLAVE_COUNT);
@ -47,21 +52,21 @@ begin
if rst = '1' then if rst = '1' then
for i in 0 to MASTER_COUNT - 1 loop for i in 0 to MASTER_COUNT - 1 loop
aw_states(i) <= AW_READY; aw_states(i) <= AW_READY;
masters_in(i).awready <= '1';
slave_in_use := (others => '0');
end loop; end loop;
awready_s <= (others => '1');
slave_in_use := (others => '0');
elsif rising_edge(clk) then elsif rising_edge(clk) then
for i in 0 to MASTER_COUNT - 1 loop -- Loop for every master for i in 0 to MASTER_COUNT - 1 loop -- Loop for every master
case aw_states(i) is case aw_states(i) is
when AW_READY => when AW_READY =>
masters_in(i).awready <= '1'; masters_in(i).awready <= '1';
if masters_out(i).awvalid = '1' and masters_in(i).awready = '1' then -- check awready. just to prevent glitches if masters_out(i).awvalid = '1' and awready_s(i) = '1' then -- check awready. just to prevent glitches
slave_idx := calculate_slave(masters_out(i).awaddr, address_array, mask_array); slave_idx := calculate_slave(masters_out(i).awaddr, address_array, mask_array);
if slave_in_use(slave_idx) /= '1' then if slave_in_use(slave_idx) /= '1' then
write_locks_s(i).slave_idx <= slave_idx; write_locks_s(i).slave_idx <= slave_idx;
write_locks_s(i).locked <= '1'; write_locks_s(i).locked <= '1';
slave_in_use(slave_idx) := '1'; slave_in_use(slave_idx) := '1';
masters_in(i).awready <= '0'; awready_s(i) <= '0';
-- output request to slave -- output request to slave
slaves_in(slave_idx).awaddr <= masters_out(i).awaddr; slaves_in(slave_idx).awaddr <= masters_out(i).awaddr;
slaves_in(slave_idx).awid <= std_logic_vector(to_unsigned(i, WID_SLAVE_BITS - WID_MASTER_BITS - 1)) & masters_out(i).awid; slaves_in(slave_idx).awid <= std_logic_vector(to_unsigned(i, WID_SLAVE_BITS - WID_MASTER_BITS - 1)) & masters_out(i).awid;