fpga/axi3-interconnect
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AXI3 crossbar interconnect
15 Commits 1 Branch 0 Tags 131 KiB
VHDL 99.3%
Shell 0.7%
4ee6195c4d
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Mario Hüttel 4ee6195c4d added resets for all signals, wrote b router
2016-08-23 17:51:22 +02:00
.settings started type definitions 2016-08-20 14:43:06 +02:00
src added resets for all signals, wrote b router 2016-08-23 17:51:22 +02:00
.gitignore started type definitions 2016-08-20 14:43:06 +02:00
.library_mapping.xml remove package body, changed aliases to subtypes 2016-08-20 18:08:38 +02:00
.project started type definitions 2016-08-20 14:43:06 +02:00