Mario Hüttel 0425710537 reset-sync

2018-04-07 19:12:55 +02:00

bench

edited simulation files

2018-04-07 19:09:27 +02:00

c

edited

2018-04-06 23:06:14 +02:00

eth

init. Works on altera

2018-04-06 17:37:39 +02:00

ws2812

init. Works on altera

2018-04-06 17:37:39 +02:00

.gitignore

init. Works on altera

2018-04-06 17:37:39 +02:00

fifo_dc.vhd

init. Works on altera

2018-04-06 17:37:39 +02:00

fifo.vhd

init. Works on altera

2018-04-06 17:37:39 +02:00

lattice_wrapper.vhd

edited

2018-04-06 23:06:14 +02:00

top.vhd

reset-sync

2018-04-07 19:12:55 +02:00

Description

No description provided

64 KiB

Languages

VHDL 91.2%

C 8.6%

Shell 0.2%