fix SPI-Slave
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660765e332
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@ -85,14 +85,13 @@ begin -- architecture RTL
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shift_reg <= (others => '0');
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dat_i_ack <= '0';
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dat_o <= (others => '0');
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miso_int <= '0';
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cnt <= 0;
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elsif rising_edge(clk) then -- rising clock edge
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dat_i_ack <= '0';
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dat_o_strb <= '0';
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if pos_edge = '1' and cs_sync = '0' then
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shift_reg <= shift_reg(DAT_WIDTH-2 downto 0) & mosi_sync;
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miso_int <= shift_reg(7);
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if cnt < DAT_WIDTH-1 then
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cnt <= cnt + 1;
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else
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@ -107,7 +106,7 @@ begin -- architecture RTL
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end if;
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end if;
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end process shifter;
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miso_int <= shift_reg(7);
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miso <= miso_int when cs = '0' else 'Z';
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end architecture RTL;
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