fpga/ws2812b-spi
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fix SPI-Slave

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This commit is contained in:
Mario Hüttel 2018-04-15 21:20:30 +02:00
parent 660765e332
commit 3c89949cb7
1 changed files with 2 additions and 3 deletions
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5
spi_slave.vhd
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@ -85,14 +85,13 @@ begin -- architecture RTL
shift_reg <= (others => '0'); shift_reg <= (others => '0');
dat_i_ack <= '0'; dat_i_ack <= '0';
dat_o <= (others => '0'); dat_o <= (others => '0');
miso_int <= '0';
cnt <= 0; cnt <= 0;
elsif rising_edge(clk) then -- rising clock edge elsif rising_edge(clk) then -- rising clock edge
dat_i_ack <= '0'; dat_i_ack <= '0';
dat_o_strb <= '0'; dat_o_strb <= '0';
if pos_edge = '1' and cs_sync = '0' then if pos_edge = '1' and cs_sync = '0' then
shift_reg <= shift_reg(DAT_WIDTH-2 downto 0) & mosi_sync; shift_reg <= shift_reg(DAT_WIDTH-2 downto 0) & mosi_sync;
miso_int <= shift_reg(7);
if cnt < DAT_WIDTH-1 then if cnt < DAT_WIDTH-1 then
cnt <= cnt + 1; cnt <= cnt + 1;
else else
@ -107,7 +106,7 @@ begin -- architecture RTL
end if; end if;
end if; end if;
end process shifter; end process shifter;
miso_int <= shift_reg(7);
miso <= miso_int when cs = '0' else 'Z'; miso <= miso_int when cs = '0' else 'Z';
end architecture RTL; end architecture RTL;