Update Makefile

Update makefile to use better syntax.

firmware/.gitignore

@@ -0,0 +1,12 @@
+*.elf
+memmap.map
+obj/
+*.creator
+*.user
+*.user*
+*.cflags
+*.cxxflags
+*.files
+*.includes
+*.config
+.qtc_clangd/*

firmware/Makefile

@@ -0,0 +1,94 @@
+################################Shimatta Makefile####################################
+#CPU:		STM32F030F4P6
+#Compiler:	arm-none-eabi
+#####################################################################################
+
+ifneq ($(VERBOSE),true)
+QUIET=@
+else
+QUIET=
+endif
+
+
+#Add Files and Folders below#########################################################
+CFILES 	= main.c syscalls/syscalls.c setup/system_init.c startup/startup_stm32f0xx.c
+CFILES += temp-adc.c
+CFILES += dmx.c
+ASFILES = sk6812.S
+INCLUDEPATH = -Iinclude -Iinclude/cmsis
+
+OBJDIR=obj
+target	= project
+LIBRARYPATH = -Lstartup
+LIBRARIES = 
+
+DEFINES = -DSTM32F030x6 -DSTM32F0XX
+mapfile = memmap
+
+##Custom Files###
+
+#TODO
+
+
+###################################################################################
+CROSS_COMPILE ?= arm-none-eabi-
+CC := $(CROSS_COMPILE)gcc
+OBJCOPY := $(CROSS_COMPILE)objcopy
+OBJDUMP := $(CROSS_COMPILE)objdump
+SIZE := $(CROSS_COMPILE)size
+
+LFLAGS = -mlittle-endian -mthumb -mcpu=cortex-m0 -mthumb-interwork 
+LFLAGS += -mfloat-abi=soft --disable-newlib-supplied-syscalls -nostartfiles
+LFLAGS += -Tstartup/stm32f030.ld -Wl,-Map=$(mapfile).map -Wl,--gc-sections -Wl,--print-memory-usage -g
+
+CFLAGS = -c -fmessage-length=0 -mlittle-endian -mthumb -mcpu=cortex-m0 -mthumb-interwork
+CFLAGS += -mfloat-abi=soft -nostartfiles -Wall -g3 -O0
+
+####################################################################################
+
+OBJ = $(CFILES:%.c=$(OBJDIR)/%.c.o)
+ASOBJ = $(ASFILES:%.S=$(OBJDIR)/%.S.o)
+
+default: $(target).elf
+
+%.bin: %.elf
+	$(OBJCOPY) -O binary $^ $@
+%.hex: %.elf
+	$(OBJCOPY) -O ihex $^ $@
+
+#Linking
+$(target).elf: $(OBJ) $(ASOBJ)
+	@echo Linking $@
+	$(QUIET)$(CC) $(LFLAGS) $(LIBRARYPATH) -o $@ $^ $(LIBRARIES)
+	$(QUIET)$(SIZE) $@
+
+#Compiling
+$(OBJ):
+	@echo [CC] $@
+	@mkdir -p $(@D)
+	$(QUIET)$(CC) $(CFLAGS) -MMD -MT $@ $(INCLUDEPATH) $(DEFINES) -o $@ $(@:$(OBJDIR)/%.c.o=%.c)
+	
+$(ASOBJ):
+	@echo [AS] $@
+	@mkdir -p $(@D)
+	$(QUIET)$(CC) $(CFLAGS) -MMD -MT $@ $(INCLUDEPATH) $(DEFINES) -o $@ $(@:$(OBJDIR)/%.S.o=%.S)
+
+.PHONY: clean mrproper objcopy disassemble binary
+
+disassemble: $(target).elf
+	$(OBJDUMP) -D -s $< > $(target).lss
+
+objcopy: $(target).bin $(target).hex
+
+mrproper:
+	rm -f $(target).pro
+
+binary: $(target).bin $(target).hex
+
+clean:
+	@echo [CLEAN] $(OBJDIR)
+	@rm -f $(target).elf $(target).bin $(target).hex $(OBJ) $(ASOBJ) $(mapfile).map $(target).lss
+	@rm -rf $(OBJDIR)/*
+
+-include $(CFILES:%.c=$(OBJDIR)/%.c.d) $(ASFILES:%.S=$(OBJDIR)/%.S.d)
+

firmware/dmx.c

@@ -0,0 +1,136 @@
+#include <ring-light/dmx.h>
+#include <stm32f0xx.h>
+
+static uint32_t dmx_base_channel;
+
+
+enum dmx_rx_state_enum {
+	DMX_RX_WAIT_FOR_BREAK = 0,
+	DMX_RX_DATA,
+};
+
+static volatile enum dmx_rx_state_enum dmx_state;
+
+
+static volatile bool break_received;
+
+/**
+ * @brief DMX data received. Contains the whole DMX universe including the first 0 byte.
+ * The controller does check the first byte to be zero.
+ */
+static volatile uint8_t dmx_channel_data[DMX_UNIVERSE_SIZE + 1];
+
+void dmx_init(uint32_t base_channel)
+{
+	int i;
+	volatile uint8_t *ptr;
+
+	for (i = 0, ptr = dmx_channel_data; i < DMX_USED_CHANNEL_COUNT; i++, ptr++) {
+		*ptr = 0u;
+	}
+
+	dmx_base_channel = base_channel;
+	break_received = false;
+
+	/* Enable GPIOA and USART1 clock */
+	RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_DMAEN;
+	RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
+
+	/* Switch RXTX pin low, activating permanent READ mode */
+	GPIOA->MODER |= (0x1<<(2*5));
+	GPIOA->BRR |= (1<<5);
+
+	/* Switch PA10 to RX alternate function of USART1 (AF1) */
+	GPIOA->MODER |= (0x2<<(2*10));
+	GPIOA->AFR[1] |=(0x1<<(4*2));
+
+	/* Set baudrate: 48MHz / 250k = 129 */
+	USART1->BRR = 192u;
+	USART1->CR3 = USART_CR3_EIE;
+	USART1->CR2 = USART_CR2_STOP_1;
+	USART1->CR1 = USART_CR1_RXNEIE | USART_CR1_RE | USART_CR1_UE;
+
+	/* Map USART1 RX to DMA Channel 3 */
+	SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_USART1RX_DMA_RMP;
+
+	DMA1_Channel3->CCR = DMA_CCR_PL_1 | DMA_CCR_MINC | DMA_CCR_TCIE;
+
+	NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
+	NVIC_EnableIRQ(USART1_IRQn);
+}
+
+
+const uint8_t *dmx_get_data()
+{
+	return (const uint8_t *)dmx_channel_data;
+}
+
+void USART1_IRQHandler(void)
+{
+	uint32_t isr;
+
+	isr = USART1->ISR;
+	USART1->ICR = USART_ICR_ORECF | USART_ICR_NCF | USART_ICR_FECF;
+
+	if (isr & USART_ISR_FE) {
+		/* Frame error received. Start of DMX frame */
+		/* Flush RX data */
+		USART1->CR3 &= ~USART_CR3_DMAR;
+		USART1->RQR = USART_RQR_RXFRQ;
+		DMA1_Channel3->CCR &= ~DMA_CCR_EN;
+		while (DMA1_Channel3->CCR & DMA_CCR_EN);
+		DMA1_Channel3->CMAR = (uint32_t)dmx_channel_data;
+		DMA1_Channel3->CPAR = (uint32_t)&USART1->RDR;
+		DMA1_Channel3->CNDTR = DMX_UNIVERSE_SIZE + 1;
+		DMA1_Channel3->CCR |= DMA_CCR_EN;
+		USART1->RQR = USART_RQR_RXFRQ;
+		USART1->CR3 |= USART_CR3_DMAR;
+		break_received = true;
+		dmx_state = DMX_RX_DATA;
+	} else if (isr & USART_ISR_RXNE) {
+		if (dmx_state != DMX_RX_DATA) {
+			USART1->RQR = USART_RQR_RXFRQ;
+		}
+	}
+
+	__DSB();
+}
+
+void DMA_CH2_3_DMA2_CH1_2_IRQHandler(void)
+{
+	uint32_t isr;
+
+	isr = DMA1->ISR;
+	/* Only clear the interupts of channel 2 (bits 11:9) */
+	DMA1->IFCR = isr & 0xF00;
+
+	if (isr & DMA_ISR_TCIF3) {
+		DMA1->ISR;
+		dmx_state = DMX_RX_WAIT_FOR_BREAK;
+	}
+	__DSB();
+}
+
+bool dmx_poll_break_received(void)
+{
+	bool ret;
+
+	/* Atomically reset the flag */
+	__disable_irq();
+	ret = break_received;
+	break_received = false;
+	__enable_irq();
+
+	return ret;
+}
+
+bool dmx_enough_data_received()
+{
+	uint32_t received_count = (DMX_UNIVERSE_SIZE + 1) - DMA1_Channel3->CNDTR;
+
+	if (received_count > (dmx_base_channel + DMX_USED_CHANNEL_COUNT)) {
+		return true;
+	}
+
+	return false;
+}

firmware/include/cmsis/core_cm0.h

@@ -0,0 +1,740 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M0
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
+#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
+
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
+  #define __STATIC_INLINE  static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI__VFP_SUPPORT____
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )		/* Cosmic */
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#endif
+
+#include <stdint.h>                      /* standard types definitions                      */
+#include <cmsis/core_cmInstr.h>                /* Core Instruction Access                         */
+#include <cmsis/core_cmFunc.h>                 /* Core Function Access                            */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+    \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_CORE  Status and Control Registers
+    \brief  Core Register type definitions.
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+    \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB     System Control Block (SCB)
+    \brief      Type definitions for the System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+    \brief      Type definitions for the System Timer Registers.
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
+                are only accessible over DAP and not via processor. Therefore
+                they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup    CMSIS_core_register
+    \defgroup   CMSIS_core_base     Core Definitions
+    \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
+    @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/** \brief  Enable External Interrupt
+
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    The function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+
+    \return             0  Interrupt status is not pending.
+    \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    The function sets the pending bit of an external interrupt.
+
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    The function clears the pending bit of an external interrupt.
+
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    The function sets the priority of an interrupt.
+
+    \note The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Interrupt number.
+    \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if((int32_t)(IRQn) < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    The function reads the priority of an interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+
+    \param [in]   IRQn  Interrupt number.
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
+                        priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if((int32_t)(IRQn) < 0) {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
+  else {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/** \brief  System Reset
+
+    The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1) { __NOP(); }                                        /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+    \brief      Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+    Counter is in free running mode to generate periodic interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts.
+
+    \return          0  Function succeeded.
+    \return          1  Function failed.
+
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+    must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

firmware/include/cmsis/core_cmFunc.h

@@ -0,0 +1,664 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+    or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Set Base Priority with condition
+
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+	or the new value increases the BASEPRI priority level.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

firmware/include/cmsis/core_cmInstr.h

@@ -0,0 +1,916 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0)
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+  return(result);
+}
+#endif
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2));
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+  result = value;                      // r will be reversed bits of v; first get LSB of v
+  for (value >>= 1; value; value >>= 1)
+  {
+    result <<= 1;
+    result |= value & 1;
+    s--;
+  }
+  result <<= s;                       // shift when v's highest bits are zero
+#endif
+  return(result);
+}
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function executes a exclusive LDR instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function executes a exclusive LDR instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function executes a exclusive LDR instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function executes a exclusive STR instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function executes a exclusive STR instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function executes a exclusive STR instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Rotate Right with Extend (32 bit)
+
+    This function moves each bit of a bitstring right by one bit.
+    The carry input is shifted in at the left end of the bitstring.
+
+    \param [in]    value  Value to rotate
+    \return               Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  LDRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/** \brief  LDRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STRT Unprivileged (8 bit)
+
+    This function executes a Unprivileged STRT instruction for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (16 bit)
+
+    This function executes a Unprivileged STRT instruction for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief  STRT Unprivileged (32 bit)
+
+    This function executes a Unprivileged STRT instruction for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

firmware/include/cmsis/core_cmSimd.h

@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.10
+ * @date     18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   // Little endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               // Big endian
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */

firmware/include/ring-light/dmx.h

@@ -0,0 +1,49 @@
+#ifndef _DMX_H_
+#define _DMX_H_
+
+
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#define DMX_UNIVERSE_SIZE (512u)
+#define DMX_USED_CHANNEL_COUNT (129u)
+
+/**
+ * @brief Init DMX reception
+ *
+ * DMX data is received from the base channel onwards:
+ * - R LED1
+ * - G LED1
+ * - B LED1
+ * - W LED1
+ * - R LED2
+ * ...
+ * - W LED32
+ * - W DISCRETE
+ *
+ * In Sum: 129 8 bit channels
+ *
+ * @param base_channel Base channel the ring light will listen on
+ */
+void dmx_init(uint32_t base_channel);
+
+/**
+ * @brief Returns the array of the 129 DMX channels
+ * @return
+ */
+const uint8_t *dmx_get_data(void);
+
+/**
+ * @brief Check if a break was received. This resets the flag
+ * @return true if a break was received since the last time calling this function
+ */
+bool dmx_poll_break_received(void);
+
+/**
+ * @brief The DMX receiver has received all data for the ring light. It can be read
+ * @return
+ */
+bool dmx_enough_data_received(void);
+
+#endif /* _DMX_H_ */

firmware/include/ring-light/temp-adc.h

@@ -0,0 +1,10 @@
+#ifndef _TEMP_ADC_H_
+#define _TEMP_ADC_H_
+
+#include <stdint.h>
+
+void temperature_adc_init(void);
+
+int32_t temperature_adc_get_temp(void);
+
+#endif /* _TEMP_ADC_H_ */

firmware/include/stm32f0xx.h

@@ -0,0 +1,244 @@
+/**
+  ******************************************************************************
+  * @file    stm32f0xx.h
+  * @author  MCD Application Team
+  * @version V2.2.2
+  * @date    26-June-2015
+  * @brief   CMSIS STM32F0xx Device Peripheral Access Layer Header File.           
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32F0xx device used in the target application
+  *              - To use or not the peripheral<61>s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral<61>s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f0xx
+  * @{
+  */
+    
+#ifndef __STM32F0xx_H
+#define __STM32F0xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+   
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/**
+  * @brief STM32 Family
+  */
+#if !defined  (STM32F0)
+#define STM32F0
+#endif /* STM32F0 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32F030x6) && !defined (STM32F030x8) &&                           \
+    !defined (STM32F031x6) && !defined (STM32F038xx) &&                           \
+    !defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
+    !defined (STM32F051x8) && !defined (STM32F058xx) &&                           \
+    !defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
+    !defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
+  /* #define STM32F030x6 */  /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes)              */
+  /* #define STM32F030x8 */  /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes)                                              */
+  /* #define STM32F031x6 */  /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes)              */
+  /* #define STM32F038xx */  /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes)                                              */
+  /* #define STM32F042x6 */  /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes)              */
+  /* #define STM32F048x6 */  /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes)                                              */
+  /* #define STM32F051x8 */  /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
+  /* #define STM32F058xx */  /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes)                                              */
+  /* #define STM32F070x6 */  /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes)                           */
+  /* #define STM32F070xB */  /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes)                          */
+  /* #define STM32F071xB */  /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes)             */
+  /* #define STM32F072xB */  /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes)             */
+  /* #define STM32F078xx */  /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes)                                             */
+  /* #define STM32F030xC */  /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes)                                             */  
+  /* #define STM32F091xC */  /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes)                                             */
+  /* #define STM32F098xx */  /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes)                                             */
+#endif
+   
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V2.2.2
+  */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
+#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32F0xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
+                                                |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
+                                                |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
+                                                |(__CMSIS_DEVICE_HAL_VERSION_RC))
+                                             
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32F030x6)
+  #include "stm32f030x6.h"
+#elif defined(STM32F030x8)
+  #include "stm32f030x8.h"
+#elif defined(STM32F031x6)
+  #include "stm32f031x6.h"
+#elif defined(STM32F038xx)
+  #include "stm32f038xx.h"
+#elif defined(STM32F042x6)
+  #include "stm32f042x6.h"
+#elif defined(STM32F048xx)
+  #include "stm32f048xx.h"
+#elif defined(STM32F051x8)
+  #include "stm32f051x8.h"
+#elif defined(STM32F058xx)
+  #include "stm32f058xx.h"
+#elif defined(STM32F070x6)
+  #include "stm32f070x6.h"
+#elif defined(STM32F070xB)
+  #include "stm32f070xb.h"
+#elif defined(STM32F071xB)
+  #include "stm32f071xb.h"
+#elif defined(STM32F072xB)
+  #include "stm32f072xb.h"
+#elif defined(STM32F078xx)
+  #include "stm32f078xx.h"
+#elif defined(STM32F091xC)
+  #include "stm32f091xc.h"
+#elif defined(STM32F098xx)
+  #include "stm32f098xx.h"
+#elif defined(STM32F030xC)
+  #include "stm32f030xc.h"    
+#else
+ #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  ERROR = 0, 
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f0xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F0xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

firmware/include/system_stm32f0xx.h

@@ -0,0 +1,121 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f0xx.h
+  * @author  MCD Application Team
+  * @version V2.2.2
+  * @date    26-June-2015
+  * @brief   CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f0xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F0XX_H
+#define __SYSTEM_STM32F0XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F0xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F0xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      3) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) by calling HAL API function HAL_RCC_ClockConfig()
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F0xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F0XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

firmware/main.c

@@ -0,0 +1,299 @@
+#include <stm32f0xx.h>
+#include <cmsis/core_cm0.h>
+#include <stdbool.h>
+#include <ring-light/temp-adc.h>
+#include <ring-light/dmx.h>
+
+#define RING_MAX_LED	32u
+#define MAX_TEMP_CELSIUS 70
+
+enum ring_modes {
+	RING_MODE_WHITE_DISCRETE,       /*!< only discrete white LEDs */
+	RING_MODE_RED,                  /*!< only red SK6812 */
+	RING_MODE_GREEN,                /*!< only green SK6812 */
+	RING_MODE_BLUE,                 /*!< only blue SK6812 */
+	RING_MODE_ALL,                  /*!< control all LEDs at once */
+	RING_MODE_ARC,                  /*!< SK6812 closing ring */
+	RING_MODE_QUARTER,              /*!< SK6812 walking quarter */
+	RING_MODE_IN_FARBE_UND_BUNT,    /*!< SK6812 color mix */
+	RING_MODE_MAX,                   /*!< end of list */
+	RING_MODE_WAIT_DMX,
+	RING_MODE_WAIT_DMX_BREAK
+};
+
+volatile int32_t temperature;
+
+extern void sk6812_send_led(uint32_t rgbw);
+
+volatile uint32_t wait_tick = 0;
+volatile bool blink_tick = false;
+
+static void wait_for_ticks(uint32_t ticks)
+{
+	wait_tick = 0;
+	while (wait_tick < ticks);
+}
+
+int main(void)
+{
+	uint32_t led_val = 0x00UL;
+	uint32_t last_led_val = 0x00UL;
+	uint32_t led_calc_val[RING_MAX_LED] = {0x00UL};
+	uint8_t led_pwm_val = 0u;
+	const uint8_t *dmx_data;
+
+	bool button_pressed = false;
+	bool force_led_update;
+	bool overtemp_flag = false;
+	enum ring_modes mode;
+
+	/* Led value / mode before going to DMX */
+	uint32_t led_val_before_dmx = 0u;
+	enum ring_modes mode_before_dmx = RING_MODE_RED; /* Init to save value */
+
+	RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN;
+	RCC->APB1ENR |= RCC_APB1ENR_TIM3EN | RCC_APB1ENR_TIM14EN;
+
+	GPIOA->MODER |= (2<<7*2)|(2<<6*2)|(1<<3*2);
+
+	/* enable pullups on encoder inputs */
+	GPIOA->PUPDR |= (1<<7*2)|(1<<6*2)|(1<<0*2);
+	/* enable TIM3 on encoder inputs */
+	GPIOA->AFR[0] |= (1<<7*4)|(1<<6*4);
+
+	/* enable PWM output for magic LED regulator */
+	GPIOB->MODER |= (2<<1*2);
+	GPIOB->AFR[0] &= ~(0<<1*4);
+
+	/*! -# init the TIM3 to read the encoder */
+	TIM3->ARR = 0xFFFF;
+	TIM3->CNT = 0;
+	TIM3->CR2 = 0;
+	TIM3->SMCR = TIM_SMCR_SMS_0;
+	TIM3->CCMR1 = TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_1;
+	TIM3->CCER = TIM_CCER_CC1P | TIM_CCER_CC2P;
+	TIM3->PSC = 0;
+	TIM3->CR1 = TIM_CR1_CEN;
+
+	/*! -# Init TIM14 for PWM control of the magic LED driver */
+	/*! -# Count up to 255 (8 bit resolution) */
+	TIM14->ARR = 0x00FFu;
+	TIM14->CNT = 0u;
+	TIM14->CCR1 = 0u;
+	/*! -# Set prescaler to 11 ==> ca. 17 KHz */
+	TIM14->PSC = 11u - 1u;
+	/*! -# PWM Mode 1 + prefetch */
+	TIM14->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE;
+	/*! -# Enable Output compare 1 */
+	TIM14->CCER = TIM_CCER_CC1E;
+	/*! -# Finally, enable TIM14 */
+	TIM14->CR2 = 0;
+	TIM14->CR1 = TIM_CR1_CEN;
+
+	/*! -# Set initial state to all 25% */
+	led_val = 64u;
+	mode    = RING_MODE_WHITE_DISCRETE;
+
+	temperature_adc_init();
+	dmx_init(0u);
+
+	SysTick_Config(800000);
+	while(1) {
+		force_led_update = false;
+		temperature = temperature_adc_get_temp();
+
+		if (led_val != last_led_val || button_pressed) {
+			force_led_update = true;
+		}
+
+		/*! -# Gradually dim down the LED brightness in case the temperature is too high */
+		if (overtemp_flag) {
+			if (temperature < (MAX_TEMP_CELSIUS-15) * 10) {
+				overtemp_flag = false;
+			}
+		} else {
+			overtemp_flag = temperature > ((MAX_TEMP_CELSIUS) * 10) ? true : false;
+		}
+		if (overtemp_flag) {
+			if (led_val > 2 && mode < RING_MODE_MAX)
+				led_val--;
+		}
+
+		if (dmx_poll_break_received()) {
+			/* DMX received. Go to DMX mode.
+			 * Save old state
+			 */
+			if (mode < RING_MODE_MAX) {
+				led_val_before_dmx = led_val;
+				mode_before_dmx = mode;
+			}
+			mode = RING_MODE_WAIT_DMX;
+		}
+
+		led_pwm_val = 0u;
+		switch (mode)
+		{
+		case RING_MODE_ALL:
+			for(int i = 0; i < RING_MAX_LED; i ++) {
+				led_calc_val[i] = (led_val << 24) + (led_val << 16) + (led_val << 8) + led_val;
+			}
+			led_pwm_val = led_val;
+			break;
+		case RING_MODE_RED:
+			for(int i = 0; i < RING_MAX_LED; i ++) {
+				led_calc_val[i] = led_val << 16;
+			}
+			break;
+		case RING_MODE_GREEN:
+			for(int i = 0; i < RING_MAX_LED; i ++) {
+				led_calc_val[i] = led_val << 24;
+			}
+			break;
+		case RING_MODE_BLUE:
+			for(int i = 0; i < RING_MAX_LED; i ++) {
+				led_calc_val[i] = led_val << 8;
+			}
+			break;
+		case RING_MODE_WHITE_DISCRETE:
+			for(int i = 0; i < RING_MAX_LED; i ++) {
+				led_calc_val[i] = 0u;
+			}
+			led_pwm_val = led_val;
+			break;
+		case RING_MODE_ARC:
+			for(int i = 0; i < RING_MAX_LED; i ++) {
+				if(led_val > i*8) {
+					led_calc_val[i] = 0xFFFFFFFFUL;
+				}
+				else {
+					led_calc_val[i] = 0x00000000UL;
+				}
+			}
+			break;
+		case RING_MODE_QUARTER:
+			for(int i = 0; i < RING_MAX_LED; i ++) {
+				if((led_val / 7 > i) && (led_val / 7 < (i + 7))) {
+					led_calc_val[i] = 0xFFFFFFFFUL;
+				}
+				else {
+					led_calc_val[i] = 0x00000000UL;
+				}
+			}
+			break;
+		case RING_MODE_IN_FARBE_UND_BUNT:
+			for(int i = 0; i < RING_MAX_LED; i ++) {
+				switch ((led_val + (i / 3)) % 3)
+				{
+				case 0:
+					led_calc_val[i] = 0x00FF0000UL;
+					break;
+				case 1:
+					led_calc_val[i] = 0xFF000000UL;
+					break;
+				case 2:
+					led_calc_val[i] = 0x0000FF00UL;
+					break;
+
+				default:
+					break;
+				}
+			}
+			break;
+		case RING_MODE_WAIT_DMX:
+			force_led_update = false;
+			if (dmx_enough_data_received() && !overtemp_flag) {
+				dmx_data = dmx_get_data();
+				mode = RING_MODE_WAIT_DMX_BREAK;
+				if (dmx_data[0] != 0)
+					break;
+				for (int i = 0; i < RING_MAX_LED; i++) {
+					led_calc_val[i] = (dmx_data[1 + i*4 + 3]) |
+							(dmx_data[1 + i*4 + 2] << 8) |
+							(dmx_data[1 + i*4 + 0] << 16) |
+							(dmx_data[1 + i*4 + 1] << 24);
+				}
+				led_pwm_val = dmx_data[129];
+				force_led_update = true;
+			} else if (overtemp_flag) {
+				force_led_update = true;
+				for (int i = 0; i < RING_MAX_LED; i++) {
+					led_calc_val[i] = 0ul;
+				}
+				led_pwm_val = 0;
+			}
+			break;
+		case RING_MODE_WAIT_DMX_BREAK:
+			force_led_update = false;
+			break;
+		default:
+			for(int i = 0; i < RING_MAX_LED; i ++) {
+				led_calc_val[i] = 0x00000000UL;
+			}
+			break;
+		}
+
+		if (overtemp_flag) {
+			force_led_update = true;
+			led_calc_val[0] = blink_tick ? 0x00FF0000UL : 0UL;
+		}
+
+		if (force_led_update) {
+			TIM14->CCR1 = led_pwm_val;
+
+			for(int i = 0; i < RING_MAX_LED; i ++) {
+				/* Allow interrupts in between LEDs.
+				 * They must not exceed the reset length of 80us of SK6812.
+				 */
+				__disable_irq();
+				sk6812_send_led(led_calc_val[i]);
+				__enable_irq();
+			}
+			last_led_val = led_val;
+		}
+
+		/* Only wait in case of non-DMX mode */
+		if (!(mode == RING_MODE_WAIT_DMX_BREAK || mode == RING_MODE_WAIT_DMX) || overtemp_flag)
+			wait_for_ticks(5);
+
+		if((int16_t)TIM3->CNT > (int16_t)led_val) {
+			led_val = 0u;
+		} else if(((int16_t)led_val - (int16_t)TIM3->CNT) > UINT8_MAX) {
+			led_val = 255u;
+		} else {
+			led_val = (int16_t)led_val - (int16_t)TIM3->CNT;
+		}
+
+		TIM3->CNT = 0u;
+
+
+		if(button_pressed) {
+			if(GPIOA->IDR & GPIO_IDR_0) {
+				button_pressed = false;
+			}
+		} else if(!(GPIOA->IDR & GPIO_IDR_0)) {
+			button_pressed = true;
+			/* Button pressed */
+			if (mode > RING_MODE_MAX) {
+				/* In DMX mode. Abort DMX mode */
+				mode = mode_before_dmx;
+				led_val = led_val_before_dmx;
+			} else {
+				/* Normal mode switching */
+				mode = (mode + 1) % RING_MODE_MAX;
+			}
+		}
+	}
+}
+
+void SysTick_Handler(void)
+{
+	static uint32_t tick = 10;
+
+	if (!--tick) {
+		tick = 10;
+		blink_tick = !blink_tick;
+	}
+
+
+	wait_tick++;
+}

firmware/setup/system_init.c

@@ -0,0 +1,104 @@
+#include <stm32f0xx.h>
+
+
+static void __init_default_clocks(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+#if defined (STM32F051x8) || defined (STM32F058x8)
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
+  RCC->CFGR &= (uint32_t)0xF8FFB80C;
+#else
+  /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
+  RCC->CFGR &= (uint32_t)0x08FFB80C;
+#endif /* STM32F051x8 or STM32F058x8 */
+  
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
+  RCC->CFGR &= (uint32_t)0xFFC0FFFF;
+
+  /* Reset PREDIV[3:0] bits */
+  RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+#if defined (STM32F072xB) || defined (STM32F078xx)
+  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
+#elif defined (STM32F071xB)
+  /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
+#elif defined (STM32F091xC) || defined (STM32F098xx)
+  /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
+#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
+  /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
+#elif defined (STM32F051x8) || defined (STM32F058xx)
+  /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
+#elif defined (STM32F042x6) || defined (STM32F048xx)
+  /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
+#elif defined (STM32F070x6) || defined (STM32F070xB)
+  /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
+  RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
+  /* Set default USB clock to PLLCLK, since there is no HSI48 */
+  RCC->CFGR3 |= (uint32_t)0x00000080;  
+#else
+ #warning "No target selected"
+#endif
+
+  /* Reset HSI14 bit */
+  RCC->CR2 &= (uint32_t)0xFFFFFFFE;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+}
+
+void __setup_clocks(void)
+{
+	uint32_t tmp;
+	
+	/* Switch PLL source to HSE OSC */
+	RCC->CFGR |= RCC_CFGR_PLLSRC;
+
+	/* Divide HSE by 2 to match HSI */
+	RCC->CFGR2 = 0x00000001;
+
+	/* Enable HSE and wait for it to become ready */
+	RCC->CR |= RCC_CR_HSEON;
+	
+	/* Wait for HSE to be ready */
+	while (!(RCC->CR & RCC_CR_HSERDY));
+
+	/* Set PLL multiplication to 12 (4 MHz * 12 = 48 MHz SysClk) */
+	RCC->CFGR |= RCC_CFGR_PLLMUL_3 | RCC_CFGR_PLLMUL_1;
+		
+	/* HSI Already running. Switch on PLL */
+	RCC->CR |= RCC_CR_PLLON;
+	
+	/* Wait for PLL to be ready */
+	while (!(RCC->CR & RCC_CR_PLLRDY));
+	
+	/* Switch System Clock to PLL */
+	tmp = RCC->CFGR;
+	tmp &= ~0x3;
+	tmp |= RCC_CFGR_SW_1;
+	RCC->CFGR = tmp;
+
+	/* Turn off HSI */
+	RCC->CR &= ~RCC_CR_HSION;
+}
+
+void __system_init(void)
+{
+
+	__init_default_clocks();
+	__setup_clocks(); 
+}

firmware/sk6812.S

@@ -0,0 +1,47 @@
+.global sk6812_send_led
+
+.equ BSRR_REGISTER, 0x48000018
+.equ PINNUM, 3
+.syntax unified
+
+sk6812_send_led:
+	push {lr}
+	push {r4, r5, r6}
+	ldr r1, =BSRR_REGISTER
+	ldr r2, =(1<<PINNUM)
+	ldr r3, =(1<<(PINNUM+16))
+	ldr r4, =32
+	ldr r5, =0x80000000
+_bitloop:
+	tst r0, r5
+	beq sk6812_send_zero	
+	bne sk6812_send_one
+_bitloop_ret:
+	lsls r0, r0, #1
+	subs r4, r4, #1
+	bne _bitloop
+	pop {r4, r5, r6}
+	pop {pc}
+	
+sk6812_send_one:
+	str r2, [r1]
+	ldr r6, =0x5
+	bl wait_r6
+	str r3, [r1]
+	ldr r6, =0x2
+	bl wait_r6
+	b _bitloop_ret
+
+sk6812_send_zero:
+	str r2, [r1]
+	ldr r6, =0x1
+	bl wait_r6
+	str r3, [r1]
+	ldr r6, =0x5
+	bl wait_r6
+	b _bitloop_ret
+	
+wait_r6:
+	subs r6, r6, #1
+	bne wait_r6
+	bx lr

firmware/startup/startup_stm32f0xx.c

@@ -0,0 +1,203 @@
+/*
+* STM32F030 Linkerscript
+* Copyright (C) 2019 Stefan Strobel <stefan.strobel@shimatta.net>
+*
+* This file is part of 'STM32F0 code template'.
+*
+* It is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, version 2 of the License.
+*
+* This code is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this template.  If not, see <http://www.gnu.org/licenses/>.
+* ------------------------------------------------------------------------
+*/
+
+/* C++ library init */
+# if defined(__cplusplus)
+extern "C" {
+	extern void __libc_init_array(void);
+}
+#endif
+
+/* Defines for weak default handlers */
+#define WEAK __attribute__((weak))
+#define ALIAS(func) __attribute__ ((weak, alias (#func)))
+
+/* Define for section mapping */
+#define SECTION(sec) __attribute__((section(sec)))
+
+/* Handler prototypes */
+#if defined(_cplusplus)
+extern "C" {
+#endif
+
+
+/* Interrupt Defualt handler */
+WEAK void __int_default_handler(void);
+
+/* Core Interrupts */
+void Reset_Handler(void);
+void NMI_Handler(void) ALIAS(__int_default_handler);
+void HardFault_Handler(void) ALIAS(__int_default_handler);
+void SVCall_Handler(void) ALIAS(__int_default_handler);
+void PendSV_Handler(void) ALIAS(__int_default_handler);
+void SysTick_Handler(void) ALIAS(__int_default_handler);
+
+/* Peripheral Interrupts (by default mapped onto Default Handler) */
+void WWDG_IRQHandler(void) ALIAS(__int_default_handler);
+void PVD_VDDIO2_IRQHandler(void) ALIAS(__int_default_handler);
+void RTC_IRQHandler(void) ALIAS(__int_default_handler);
+void FLASH_IRQHandler(void) ALIAS(__int_default_handler);
+void RCC_CRS_IRQHandler(void) ALIAS(__int_default_handler);
+void EXTI0_1_IRQHandler(void) ALIAS(__int_default_handler);
+void EXTI2_3_IRQHandler(void) ALIAS(__int_default_handler);
+void EXTI4_15_IRQHandler(void) ALIAS(__int_default_handler);
+void TSC_IRWHandler(void) ALIAS(__int_default_handler);
+void DMA_CH1_IRQHandler(void) ALIAS(__int_default_handler);
+void DMA_CH2_3_DMA2_CH1_2_IRQHandler(void) ALIAS(__int_default_handler);
+void DMA_CH4_5_6_7_DMA2_CH3_4_5_IRQHandler(void) ALIAS(__int_default_handler);
+void ADC_COMP_IRQHandler(void) ALIAS(__int_default_handler);
+void TIM1_BRK_UP_TRG_COM_IRQHandler(void) ALIAS(__int_default_handler);
+void TIM1_CC_IRQHandler(void) ALIAS(__int_default_handler);
+void TIM2_IRQHandler(void) ALIAS(__int_default_handler);
+void TIM3_IRQHandler(void) ALIAS(__int_default_handler);
+void TIM6_DAC_IRQHandler(void) ALIAS(__int_default_handler);
+void TIM7_IRQHandler(void) ALIAS(__int_default_handler);
+void TIM14_IRQHandler(void) ALIAS(__int_default_handler);
+void TIM15_IRQHandler(void) ALIAS(__int_default_handler);
+void TIM16_IRQHandler(void) ALIAS(__int_default_handler);
+void TIM17_IRQHandler(void) ALIAS(__int_default_handler);
+void I2C1_IRQHandler(void) ALIAS(__int_default_handler);
+void I2C2_IRQHandler(void) ALIAS(__int_default_handler);
+void SPI1_IRQHandler(void) ALIAS(__int_default_handler);
+void SPI2_IRQHandler(void) ALIAS(__int_default_handler);
+void USART1_IRQHandler(void) ALIAS(__int_default_handler);
+void USART2_IRQHandler(void) ALIAS(__int_default_handler);
+void USART3_4_5_6_7_8_IRQHandler(void) ALIAS(__int_default_handler);
+void CEC_CAN_IRQHandler(void) ALIAS(__int_default_handler);
+void USB_IRQHandler(void) ALIAS(__int_default_handler);
+    
+
+extern int main(void);
+extern void __system_init(void);
+
+extern void __ld_top_of_stack(void);
+#if defined(_cplusplus)
+extern "C" }
+#endif
+
+void (* const vector_table[])(void) SECTION(".vectors") = {
+	&__ld_top_of_stack,
+	/* Core Interrupts */
+	Reset_Handler,
+	NMI_Handler,
+	HardFault_Handler,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	SVCall_Handler,
+	0,
+	0,
+	PendSV_Handler,
+	SysTick_Handler,
+	/* Peripheral Interrupts */
+	WWDG_IRQHandler,
+	PVD_VDDIO2_IRQHandler,
+	RTC_IRQHandler,
+	FLASH_IRQHandler,
+	RCC_CRS_IRQHandler,
+	EXTI0_1_IRQHandler,
+	EXTI2_3_IRQHandler,
+	EXTI4_15_IRQHandler,
+	TSC_IRWHandler,
+	DMA_CH1_IRQHandler,
+	DMA_CH2_3_DMA2_CH1_2_IRQHandler,
+	DMA_CH4_5_6_7_DMA2_CH3_4_5_IRQHandler,
+	ADC_COMP_IRQHandler,
+	TIM1_BRK_UP_TRG_COM_IRQHandler,
+	TIM1_CC_IRQHandler,
+	TIM2_IRQHandler,
+	TIM3_IRQHandler,
+	TIM6_DAC_IRQHandler,
+	TIM7_IRQHandler,
+	TIM14_IRQHandler,
+	TIM15_IRQHandler,
+	TIM16_IRQHandler,
+	TIM17_IRQHandler,
+	I2C1_IRQHandler,
+	I2C2_IRQHandler,
+	SPI1_IRQHandler,
+	SPI2_IRQHandler,
+	USART1_IRQHandler,
+	USART2_IRQHandler,
+	USART3_4_5_6_7_8_IRQHandler,
+	CEC_CAN_IRQHandler,
+	USB_IRQHandler,
+};
+
+static void __init_section(unsigned int *src_start, unsigned int *dest_start, unsigned int *dest_end) {
+	unsigned int *get, *put;
+	
+	put = dest_start;
+	get = src_start;
+	
+	while ((unsigned int)put < (unsigned int)dest_end) {
+		*(put++) = *(get++);	
+	}
+}
+
+static void __fill_zero(unsigned int *start, unsigned int *end) {
+	while ((unsigned int) start < (unsigned int)end) {
+		*(start++) = 0x00000000;	
+	}
+}
+
+extern unsigned int __ld_load_data;
+extern unsigned int __ld_sitcm;
+extern unsigned int __ld_eitcm;
+extern unsigned int __ld_sdtcm;
+extern unsigned int __ld_edtcm;
+extern unsigned int __ld_sdata;
+extern unsigned int __ld_edata;
+extern unsigned int __ld_sbss;
+extern unsigned int __ld_ebss;
+extern unsigned int __ld_sheap;
+extern unsigned int __ld_eheap;
+
+void Reset_Handler(void) {
+	/* Stack is already initilized by hardware */
+
+	/* Copy .data section */
+	__init_section(&__ld_load_data, &__ld_sdata, &__ld_edata);
+	/* Fill bss with zero */
+	__fill_zero(&__ld_sbss, &__ld_ebss);
+	/* Fill Heap with zero */
+	__fill_zero(&__ld_sheap, &__ld_eheap);
+	/* Set clocks, waitstates, ART operation etc. */
+	__system_init();
+	
+	/* C++ init function */
+#if defined(__cplusplus)
+	__libc_init_array();
+#endif
+	/* Call main */
+	main();	
+	
+	/* Catch return from main() */
+	while(1);
+}
+
+WEAK void __int_default_handler(void)
+{
+	while(1);
+}

firmware/startup/stm32f030.ld

@@ -0,0 +1,133 @@
+/*
+* STM32F030 Linkerscript
+* Copyright (C) 2019 Stefan Strobel <stefan.strobel@shimatta.net>
+*
+* This file is part of 'STM32F0 code template'.
+*
+* It is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, version 2 of the License.
+*
+* This code is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this template.  If not, see <http://www.gnu.org/licenses/>.
+* --------------------------------------------------------------------
+* FLASH: 16K
+* RAM: 4K
+*/
+
+/* USER PARAMETERS */
+__ld_stack_size = 0x0400;
+__ld_heap_size  = 0x0200;
+
+/* END OF USER PARAMETERS */
+ENTRY(Reset_Handler)
+__ld_top_of_stack = 0x20001000; /* One byte above the end of the SRAM. Stack is pre-decrewmenting, so this is okay */
+
+
+/* Available memory areas */
+MEMORY
+{
+	FLASH (xr)	: ORIGIN = 0x08000000, LENGTH = 16K
+	RAM (xrw)	: ORIGIN = 0x20000000, LENGTH = 4K	
+}
+
+SECTIONS
+{
+	.vectors : ALIGN(4)
+	{
+		KEEP(*(.vectors))
+		. = ALIGN(4);
+	} >FLASH
+	
+	.text : ALIGN(4)
+	{
+		*(.text)           /* .text sections (code) */
+    		*(.text*)          /* .text* sections (code) */
+    		*(.rodata)         /* .rodata sections (constants, strings, etc.) */
+    		*(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
+    		*(.glue_7)         /* glue arm to thumb code */
+    		*(.glue_7t)        /* glue thumb to arm code */
+		*(.eh_frame)
+		KEEP(*(.init))	   /* Constructors */
+		KEEP(*(.fini))     /* Destructors  */
+		. = ALIGN(4);
+	} >FLASH =0xFF
+	
+	.ARM.extab : ALIGN(4)
+	{ 
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+		. = ALIGN(4);
+	} >FLASH =0xFF
+	
+	.ARM : ALIGN(4)
+	{
+    		__exidx_start = .;
+      		*(.ARM.exidx*)
+      		__exidx_end = .;
+      		. = ALIGN(4);
+   	} >FLASH =0xFF
+	
+	/* Constructor/Destructor tables */
+ 	.preinit_array : ALIGN(4)
+	{
+    		PROVIDE_HIDDEN (__preinit_array_start = .);
+    		KEEP (*(.preinit_array*))
+    		PROVIDE_HIDDEN (__preinit_array_end = .);
+		. = ALIGN(4);
+  	} >FLASH =0xFF
+  	
+	.init_array : ALIGN(4)
+  	{
+    		PROVIDE_HIDDEN (__init_array_start = .);
+    		KEEP (*(SORT(.init_array.*)))
+    		KEEP (*(.init_array*))
+    		PROVIDE_HIDDEN (__init_array_end = .);
+		. = ALIGN(4);
+  	} >FLASH =0xFF
+  
+	.fini_array : ALIGN(4)
+	{
+    		PROVIDE_HIDDEN (__fini_array_start = .);
+    		KEEP (*(.fini_array*))
+    		KEEP (*(SORT(.fini_array.*)))
+    		PROVIDE_HIDDEN (__fini_array_end = .);
+		. = ALIGN(4);
+  	} >FLASH =0xFF
+	
+	/* Initialized Data */
+	__ld_load_data = LOADADDR(.data);
+	.data : ALIGN(4)
+	{
+		__ld_sdata = .;
+		*(.data)
+		*(.data*)
+		. = ALIGN(4);
+		__ld_edata = .;
+	} >RAM AT> FLASH
+	
+	/* Uninitialized static data */
+	.bss : ALIGN(4)
+	{
+		__ld_sbss = .;
+		*(.bss)
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__ld_ebss = .;
+	} >RAM
+
+	.heap_stack (NOLOAD) : ALIGN(4)
+	{
+		__ld_sheap = .;
+		. = . + __ld_heap_size;
+		__ld_eheap = .;
+		. = . + __ld_stack_size;
+		. = ALIGN(4);
+	} >RAM
+}
+

firmware/syscalls/syscalls.c

@@ -0,0 +1,47 @@
+/*
+ * syscalls.c
+ *
+ *  Created on: Dec 14, 2014
+ *      Author: Mario Huettel <mario.huettel@gmx.net>
+ */
+
+            extern char __ld_sheap;    // Defined by the linker
+            extern char __ld_eheap;
+char* _sbrk(int incr) {
+
+            static char *heap_end;
+            char *prev_heap_end;
+
+            if (heap_end == 0) {
+              heap_end = &__ld_sheap;
+            }
+            prev_heap_end = heap_end;
+            if (heap_end + incr > &__ld_eheap) {
+              return 0;
+            }
+
+            heap_end += incr;
+            return (char*) prev_heap_end;
+          }
+int _isatty(int fd) {
+	return 1;
+}
+int _close(int fd) {
+	return 0;
+}
+int _open(int fd) {
+	return 0;
+}
+int _fstat(void) {
+	return 0;
+}
+int _lseek(void) {
+	return 0;
+}
+int _read(void) {
+	return 0;
+}
+int _write(int fd, const void *buf, int count) {
+	//sendString((char*)buf, count);
+	return count;
+}

firmware/temp-adc.c

@@ -0,0 +1,104 @@
+#include <ring-light/temp-adc.h>
+#include <stm32f0xx.h>
+
+#define FLOAT_TO_S23_8(x) (int32_t)((x) * 1024.0f)
+
+static volatile uint16_t adc_results[16];
+static volatile int32_t vdd_lf_s23_8 = FLOAT_TO_S23_8(0);
+static volatile int32_t temp_lf_s23_8 = FLOAT_TO_S23_8(0);
+
+void temperature_adc_init(void)
+{
+	RCC->AHBENR |= RCC_AHBENR_DMAEN;
+	RCC->APB2ENR |= RCC_APB2ENR_ADCEN;
+
+	/* ADC is mapped to DMA Channel 1 */
+	SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_DMA_RMP;
+
+	DMA1_Channel1->CNDTR = 16;
+	DMA1_Channel1->CPAR = (uint32_t)&ADC1->DR;
+	DMA1_Channel1->CMAR = (uint32_t)&adc_results[0];
+	DMA1_Channel1->CCR = DMA_CCR_PL_1 | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 | DMA_CCR_MINC | DMA_CCR_CIRC | DMA_CCR_TCIE | DMA_CCR_EN;
+
+	NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+
+	/* Calibrate the ADC */
+	ADC1->CR = ADC_CR_ADCAL;
+	while (ADC1->CR & ADC_CR_ADCAL);
+
+	/* Dummy read the offset calibration value */
+	ADC1->DR;
+	ADC1->CR = 0;
+	ADC1->CFGR1 = ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_CONT;
+	ADC1->CFGR2 = ADC_CFGR2_CKMODE_1;
+	ADC1->SMPR = 7u;
+	ADC->CCR |= ADC_CCR_TSEN | ADC_CCR_VREFEN;
+	ADC1->CHSELR = (1<<17) | (1<<16);
+	ADC1->CR = ADC_CR_ADEN | ADC_CR_ADSTART;
+}
+
+static uint32_t get_temp_sensor_cal(void)
+{
+	const volatile uint16_t *cal;
+
+	cal = (const volatile uint16_t *)0x1FFFF7B8UL;
+	return (uint32_t)*cal;
+}
+
+int32_t temperature_adc_get_temp(void)
+{
+	int32_t temp;
+	const int32_t slope = FLOAT_TO_S23_8(5.336f);
+
+
+	temp = ((temp_lf_s23_8 / 16) * vdd_lf_s23_8 / FLOAT_TO_S23_8(3.3)) * 16;
+	temp = (get_temp_sensor_cal() << 10) - temp;
+	temp = (temp * 10 / slope) + 300;
+
+	return temp;
+}
+
+static uint32_t get_vrefint_cal(void)
+{
+	const volatile uint16_t *cal;
+
+	cal = (const volatile uint16_t *)0x1FFFF7BAUL;
+	return (uint32_t)*cal;
+}
+
+static void process_adc_samples(void)
+{
+	int i;
+	uint32_t temp_val = 0;
+	uint32_t vref_val = 0;
+	int32_t vdd_s23_8;
+	int32_t temp_s23_8;
+	const uint32_t ref_cal = get_vrefint_cal();
+
+	for (i = 0; i < 8; i++) {
+		temp_val += adc_results[2 * i];
+		vref_val += adc_results[(2 * i) + 1];
+	}
+
+	vref_val >>= 3;
+	temp_val >>= 3;
+
+	vdd_s23_8 =  (FLOAT_TO_S23_8(3.3f) * ref_cal) / vref_val;
+	temp_s23_8 = temp_val << 10;
+
+	/* Moving average filter */
+	vdd_lf_s23_8 = (vdd_lf_s23_8 * FLOAT_TO_S23_8(0.78125f) + vdd_s23_8 * FLOAT_TO_S23_8(0.21875f)) >> 10;
+	temp_lf_s23_8 = (int32_t)((((int64_t)temp_lf_s23_8 * (int64_t)FLOAT_TO_S23_8(0.78125f)) + temp_s23_8 * FLOAT_TO_S23_8(0.21875f)) / 1024);
+}
+
+void DMA_CH1_IRQHandler(void)
+{
+	uint32_t isr;
+	
+	isr = DMA1->ISR;
+	DMA1->IFCR = isr & 0xF;
+
+	if (isr & DMA_ISR_TCIF1) {
+		process_adc_samples();
+	}
+}

housing/.gitignore

@@ -1 +1,2 @@
 *.FCStd?
+*.stl

pcb/WhiteLEDs.sch

@@ -0,0 +1,939 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 3 3
+Title "Microscope LED Ring Light"
+Date "2021-04-09"
+Rev "v2.1"
+Comp "Shimatta"
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L power:+12V #PWR0135
+U 1 1 606A95A3
+P 2800 2300
+F 0 "#PWR0135" H 2800 2150 50  0001 C CNN
+F 1 "+12V" H 2815 2473 50  0000 C CNN
+F 2 "" H 2800 2300 50  0001 C CNN
+F 3 "" H 2800 2300 50  0001 C CNN
+	1    2800 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L shimatta_regulators:LP8867 U6
+U 1 1 606038B7
+P 3000 2650
+F 0 "U6" H 3375 2815 50  0000 C CNN
+F 1 "LP8867C-Q1" H 3375 2724 50  0000 C CNN
+F 2 "shimatta_smd:Texas_PWP-PDSO-G20" H 3000 2650 50  0001 C CNN
+F 3 "" H 3000 2650 50  0001 C CNN
+	1    3000 2650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2900 2750 2800 2750
+Wire Wire Line
+	2900 2850 2800 2850
+Wire Wire Line
+	2800 2850 2800 2750
+Connection ~ 2800 2750
+Wire Wire Line
+	2800 2300 2800 2400
+$Comp
+L Device:C C53
+U 1 1 60607491
+P 2000 2600
+F 0 "C53" H 2115 2646 50  0000 L CNN
+F 1 "10u" H 2115 2555 50  0000 L CNN
+F 2 "Capacitor_SMD:C_1210_3225Metric" H 2038 2450 50  0001 C CNN
+F 3 "~" H 2000 2600 50  0001 C CNN
+	1    2000 2600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2800 2400 2350 2400
+Wire Wire Line
+	2000 2400 2000 2450
+Connection ~ 2800 2400
+Wire Wire Line
+	2800 2400 2800 2750
+Wire Wire Line
+	2000 2750 2000 2800
+$Comp
+L power:GND #PWR0137
+U 1 1 60609BF1
+P 2000 2800
+F 0 "#PWR0137" H 2000 2550 50  0001 C CNN
+F 1 "GND" H 2005 2627 50  0000 C CNN
+F 2 "" H 2000 2800 50  0001 C CNN
+F 3 "" H 2000 2800 50  0001 C CNN
+	1    2000 2800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3300 4050 3300 4100
+Wire Wire Line
+	3300 4100 3400 4100
+Wire Wire Line
+	3600 4100 3600 4050
+Wire Wire Line
+	3500 4050 3500 4100
+Connection ~ 3500 4100
+Wire Wire Line
+	3500 4100 3600 4100
+Wire Wire Line
+	3400 4050 3400 4100
+Connection ~ 3400 4100
+Wire Wire Line
+	3400 4100 3450 4100
+Wire Wire Line
+	3450 4100 3450 4200
+Connection ~ 3450 4100
+Wire Wire Line
+	3450 4100 3500 4100
+$Comp
+L power:GND #PWR0145
+U 1 1 6060B47A
+P 3450 4200
+F 0 "#PWR0145" H 3450 3950 50  0001 C CNN
+F 1 "GND" H 3455 4027 50  0000 C CNN
+F 2 "" H 3450 4200 50  0001 C CNN
+F 3 "" H 3450 4200 50  0001 C CNN
+	1    3450 4200
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2900 3300 2850 3300
+Wire Wire Line
+	2850 3300 2850 3000
+Connection ~ 2850 3000
+Wire Wire Line
+	2850 3000 2900 3000
+$Comp
+L power:+3V3 #PWR0134
+U 1 1 6060D6F8
+P 1850 2300
+F 0 "#PWR0134" H 1850 2150 50  0001 C CNN
+F 1 "+3V3" H 1865 2473 50  0000 C CNN
+F 2 "" H 1850 2300 50  0001 C CNN
+F 3 "" H 1850 2300 50  0001 C CNN
+	1    1850 2300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1850 2300 1850 3000
+Wire Wire Line
+	1850 3000 2850 3000
+Wire Wire Line
+	2900 3500 1850 3500
+Wire Wire Line
+	1850 3500 1850 4500
+$Comp
+L Device:R R12
+U 1 1 6060F6AC
+P 1850 4650
+F 0 "R12" H 1920 4696 50  0000 L CNN
+F 1 "39k" H 1920 4605 50  0000 L CNN
+F 2 "Resistor_SMD:R_0603_1608Metric" V 1780 4650 50  0001 C CNN
+F 3 "~" H 1850 4650 50  0001 C CNN
+	1    1850 4650
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1850 4800 1850 4950
+$Comp
+L power:GND #PWR0143
+U 1 1 60610BC6
+P 1850 4950
+F 0 "#PWR0143" H 1850 4700 50  0001 C CNN
+F 1 "GND" H 1855 4777 50  0000 C CNN
+F 2 "" H 1850 4950 50  0001 C CNN
+F 3 "" H 1850 4950 50  0001 C CNN
+	1    1850 4950
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2900 3600 2150 3600
+Wire Wire Line
+	2150 3600 2150 3700
+$Comp
+L Device:C C58
+U 1 1 60611FE7
+P 2150 3850
+F 0 "C58" H 2265 3896 50  0000 L CNN
+F 1 "1u" H 2265 3805 50  0000 L CNN
+F 2 "Capacitor_SMD:C_0805_2012Metric" H 2188 3700 50  0001 C CNN
+F 3 "~" H 2150 3850 50  0001 C CNN
+	1    2150 3850
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2150 4000 2150 4150
+$Comp
+L power:GND #PWR0144
+U 1 1 60616F05
+P 2150 4150
+F 0 "#PWR0144" H 2150 3900 50  0001 C CNN
+F 1 "GND" H 2155 3977 50  0000 C CNN
+F 2 "" H 2150 4150 50  0001 C CNN
+F 3 "" H 2150 4150 50  0001 C CNN
+	1    2150 4150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2900 3400 950  3400
+Text HLabel 950  3400 0    50   Input ~ 0
+PWM
+$Comp
+L Device:R R11
+U 1 1 6061C45B
+P 1500 3850
+F 0 "R11" H 1430 3804 50  0000 R CNN
+F 1 "56k" H 1430 3895 50  0000 R CNN
+F 2 "Resistor_SMD:R_0603_1608Metric" V 1430 3850 50  0001 C CNN
+F 3 "~" H 1500 3850 50  0001 C CNN
+	1    1500 3850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	1500 4000 1500 4150
+$Comp
+L power:GND #PWR0142
+U 1 1 60621494
+P 1500 4150
+F 0 "#PWR0142" H 1500 3900 50  0001 C CNN
+F 1 "GND" H 1505 3977 50  0000 C CNN
+F 2 "" H 1500 4150 50  0001 C CNN
+F 3 "" H 1500 4150 50  0001 C CNN
+	1    1500 4150
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	1500 3700 1500 3100
+NoConn ~ 2900 3200
+NoConn ~ 2900 3750
+NoConn ~ 2900 3850
+$Comp
+L Device:L_Core_Ferrite L2
+U 1 1 60625C92
+P 3350 2400
+F 0 "L2" V 3575 2400 50  0000 C CNN
+F 1 "45223C" V 3484 2400 50  0000 C CNN
+F 2 "shimatta_inductor:Murata_4500" H 3350 2400 50  0001 C CNN
+F 3 "https://www.mouser.de/datasheet/2/281/kmp_4500-1858591.pdf" H 3350 2400 50  0001 C CNN
+	1    3350 2400
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
+	3850 2750 4100 2750
+$Comp
+L Device:C C54
+U 1 1 60634347
+P 2350 2600
+F 0 "C54" H 2465 2646 50  0000 L CNN
+F 1 "10u" H 2465 2555 50  0000 L CNN
+F 2 "Capacitor_SMD:C_1210_3225Metric" H 2388 2450 50  0001 C CNN
+F 3 "~" H 2350 2600 50  0001 C CNN
+	1    2350 2600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2350 2450 2350 2400
+Connection ~ 2350 2400
+Wire Wire Line
+	2350 2400 2000 2400
+Wire Wire Line
+	2350 2750 2350 2800
+$Comp
+L power:GND #PWR0138
+U 1 1 60638E9E
+P 2350 2800
+F 0 "#PWR0138" H 2350 2550 50  0001 C CNN
+F 1 "GND" H 2355 2627 50  0000 C CNN
+F 2 "" H 2350 2800 50  0001 C CNN
+F 3 "" H 2350 2800 50  0001 C CNN
+	1    2350 2800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2800 2400 3200 2400
+Wire Wire Line
+	4100 2400 4100 2750
+Wire Wire Line
+	3500 2400 4100 2400
+Wire Wire Line
+	4100 2400 4500 2400
+Connection ~ 4100 2400
+$Comp
+L Device:D_Schottky D33
+U 1 1 6063DA61
+P 4650 2400
+F 0 "D33" H 4650 2183 50  0000 C CNN
+F 1 "MBRA160T3G" H 4650 2274 50  0000 C CNN
+F 2 "Diode_SMD:D_SMA" H 4650 2400 50  0001 C CNN
+F 3 "https://www.tme.eu/Document/188728c22b8ff1520f089004a837a136/MBRA160T3G.PDF" H 4650 2400 50  0001 C CNN
+	1    4650 2400
+	-1   0    0    1   
+$EndComp
+$Comp
+L Device:C C55
+U 1 1 60641C4C
+P 4900 2600
+F 0 "C55" H 5015 2646 50  0000 L CNN
+F 1 "10u" H 5015 2555 50  0000 L CNN
+F 2 "Capacitor_SMD:C_1210_3225Metric" H 4938 2450 50  0001 C CNN
+F 3 "~" H 4900 2600 50  0001 C CNN
+	1    4900 2600
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:C C56
+U 1 1 60642ABF
+P 5250 2600
+F 0 "C56" H 5365 2646 50  0000 L CNN
+F 1 "10u" H 5365 2555 50  0000 L CNN
+F 2 "Capacitor_SMD:C_1210_3225Metric" H 5288 2450 50  0001 C CNN
+F 3 "~" H 5250 2600 50  0001 C CNN
+	1    5250 2600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5250 2450 5250 2400
+Wire Wire Line
+	4800 2400 4900 2400
+Wire Wire Line
+	4900 2450 4900 2400
+Connection ~ 4900 2400
+Wire Wire Line
+	4900 2400 5100 2400
+Wire Wire Line
+	4900 2750 4900 2800
+Wire Wire Line
+	5250 2750 5250 2800
+$Comp
+L power:GND #PWR0139
+U 1 1 60646C16
+P 4900 2800
+F 0 "#PWR0139" H 4900 2550 50  0001 C CNN
+F 1 "GND" H 4905 2627 50  0000 C CNN
+F 2 "" H 4900 2800 50  0001 C CNN
+F 3 "" H 4900 2800 50  0001 C CNN
+	1    4900 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L power:GND #PWR0140
+U 1 1 6064788D
+P 5250 2800
+F 0 "#PWR0140" H 5250 2550 50  0001 C CNN
+F 1 "GND" H 5255 2627 50  0000 C CNN
+F 2 "" H 5250 2800 50  0001 C CNN
+F 3 "" H 5250 2800 50  0001 C CNN
+	1    5250 2800
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5250 2400 5800 2400
+Connection ~ 5250 2400
+$Comp
+L Device:R R10
+U 1 1 6064ADF7
+P 5800 3000
+F 0 "R10" V 5593 3000 50  0000 C CNN
+F 1 "100k" V 5684 3000 50  0000 C CNN
+F 2 "Resistor_SMD:R_0603_1608Metric" V 5730 3000 50  0001 C CNN
+F 3 "~" H 5800 3000 50  0001 C CNN
+	1    5800 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:R R9
+U 1 1 6064B526
+P 5800 2600
+F 0 "R9" V 5593 2600 50  0000 C CNN
+F 1 "560k" V 5684 2600 50  0000 C CNN
+F 2 "Resistor_SMD:R_0603_1608Metric" V 5730 2600 50  0001 C CNN
+F 3 "~" H 5800 2600 50  0001 C CNN
+	1    5800 2600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5800 2750 5800 2800
+Wire Wire Line
+	4750 3050 4750 2850
+Wire Wire Line
+	4750 2850 3850 2850
+Connection ~ 5800 2800
+Wire Wire Line
+	5800 2800 5800 2850
+Wire Wire Line
+	5800 3150 5800 3200
+$Comp
+L power:GND #PWR0141
+U 1 1 606534A7
+P 5800 3200
+F 0 "#PWR0141" H 5800 2950 50  0001 C CNN
+F 1 "GND" H 5805 3027 50  0000 C CNN
+F 2 "" H 5800 3200 50  0001 C CNN
+F 3 "" H 5800 3200 50  0001 C CNN
+	1    5800 3200
+	1    0    0    -1  
+$EndComp
+$Comp
+L Device:C C57
+U 1 1 60654433
+P 6000 2600
+F 0 "C57" H 6115 2646 50  0000 L CNN
+F 1 "14p" H 6115 2555 50  0000 L CNN
+F 2 "Capacitor_SMD:C_0603_1608Metric" H 6038 2450 50  0001 C CNN
+F 3 "~" H 6000 2600 50  0001 C CNN
+	1    6000 2600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6000 2750 6000 2800
+Wire Wire Line
+	6000 2800 5800 2800
+Wire Wire Line
+	6000 2450 6000 2400
+Wire Wire Line
+	6000 2400 5800 2400
+Connection ~ 5800 2400
+Wire Wire Line
+	5800 2400 5800 2450
+$Comp
+L Device:LED D34
+U 1 1 6065A89F
+P 6450 2600
+F 0 "D34" V 6489 2482 50  0000 R CNN
+F 1 "LED" V 6398 2482 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6450 2600 50  0001 C CNN
+F 3 "~" H 6450 2600 50  0001 C CNN
+	1    6450 2600
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D35
+U 1 1 6065AC27
+P 6750 2600
+F 0 "D35" V 6789 2482 50  0000 R CNN
+F 1 "LED" V 6698 2482 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6750 2600 50  0001 C CNN
+F 3 "~" H 6750 2600 50  0001 C CNN
+	1    6750 2600
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D36
+U 1 1 6065B1C6
+P 7050 2600
+F 0 "D36" V 7089 2482 50  0000 R CNN
+F 1 "LED" V 6998 2482 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7050 2600 50  0001 C CNN
+F 3 "~" H 7050 2600 50  0001 C CNN
+	1    7050 2600
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D37
+U 1 1 6065B693
+P 7350 2600
+F 0 "D37" V 7389 2482 50  0000 R CNN
+F 1 "LED" V 7298 2482 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7350 2600 50  0001 C CNN
+F 3 "~" H 7350 2600 50  0001 C CNN
+	1    7350 2600
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
+	4750 3050 5400 3050
+Wire Wire Line
+	5400 3050 5400 2800
+Wire Wire Line
+	5400 2800 5800 2800
+Wire Wire Line
+	6000 2400 6450 2400
+Wire Wire Line
+	7350 2400 7350 2450
+Connection ~ 6000 2400
+Wire Wire Line
+	7050 2450 7050 2400
+Connection ~ 7050 2400
+Wire Wire Line
+	7050 2400 7350 2400
+Wire Wire Line
+	6750 2400 6750 2450
+Connection ~ 6750 2400
+Wire Wire Line
+	6750 2400 7050 2400
+Wire Wire Line
+	6450 2450 6450 2400
+Connection ~ 6450 2400
+Wire Wire Line
+	6450 2400 6750 2400
+$Comp
+L Device:LED D38
+U 1 1 6068EE55
+P 6450 2950
+F 0 "D38" V 6489 2832 50  0000 R CNN
+F 1 "LED" V 6398 2832 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6450 2950 50  0001 C CNN
+F 3 "~" H 6450 2950 50  0001 C CNN
+	1    6450 2950
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D39
+U 1 1 6068EF77
+P 6750 2950
+F 0 "D39" V 6789 2832 50  0000 R CNN
+F 1 "LED" V 6698 2832 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6750 2950 50  0001 C CNN
+F 3 "~" H 6750 2950 50  0001 C CNN
+	1    6750 2950
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D40
+U 1 1 6068EF81
+P 7050 2950
+F 0 "D40" V 7089 2832 50  0000 R CNN
+F 1 "LED" V 6998 2832 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7050 2950 50  0001 C CNN
+F 3 "~" H 7050 2950 50  0001 C CNN
+	1    7050 2950
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D41
+U 1 1 6068EF8B
+P 7350 2950
+F 0 "D41" V 7389 2832 50  0000 R CNN
+F 1 "LED" V 7298 2832 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7350 2950 50  0001 C CNN
+F 3 "~" H 7350 2950 50  0001 C CNN
+	1    7350 2950
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
+	6450 2800 6450 2750
+Wire Wire Line
+	6750 2750 6750 2800
+Wire Wire Line
+	7050 2800 7050 2750
+Wire Wire Line
+	7350 2750 7350 2800
+$Comp
+L Device:LED D42
+U 1 1 6069A38D
+P 6450 3300
+F 0 "D42" V 6489 3182 50  0000 R CNN
+F 1 "LED" V 6398 3182 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6450 3300 50  0001 C CNN
+F 3 "~" H 6450 3300 50  0001 C CNN
+	1    6450 3300
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D43
+U 1 1 6069A567
+P 6750 3300
+F 0 "D43" V 6789 3182 50  0000 R CNN
+F 1 "LED" V 6698 3182 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6750 3300 50  0001 C CNN
+F 3 "~" H 6750 3300 50  0001 C CNN
+	1    6750 3300
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D44
+U 1 1 6069A571
+P 7050 3300
+F 0 "D44" V 7089 3182 50  0000 R CNN
+F 1 "LED" V 6998 3182 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7050 3300 50  0001 C CNN
+F 3 "~" H 7050 3300 50  0001 C CNN
+	1    7050 3300
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D45
+U 1 1 6069A57B
+P 7350 3300
+F 0 "D45" V 7389 3182 50  0000 R CNN
+F 1 "LED" V 7298 3182 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7350 3300 50  0001 C CNN
+F 3 "~" H 7350 3300 50  0001 C CNN
+	1    7350 3300
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D46
+U 1 1 6069A585
+P 6450 3650
+F 0 "D46" V 6489 3532 50  0000 R CNN
+F 1 "LED" V 6398 3532 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6450 3650 50  0001 C CNN
+F 3 "~" H 6450 3650 50  0001 C CNN
+	1    6450 3650
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D47
+U 1 1 6069A58F
+P 6750 3650
+F 0 "D47" V 6789 3532 50  0000 R CNN
+F 1 "LED" V 6698 3532 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6750 3650 50  0001 C CNN
+F 3 "~" H 6750 3650 50  0001 C CNN
+	1    6750 3650
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D48
+U 1 1 6069A599
+P 7050 3650
+F 0 "D48" V 7089 3532 50  0000 R CNN
+F 1 "LED" V 6998 3532 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7050 3650 50  0001 C CNN
+F 3 "~" H 7050 3650 50  0001 C CNN
+	1    7050 3650
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D49
+U 1 1 6069A5A3
+P 7350 3650
+F 0 "D49" V 7389 3532 50  0000 R CNN
+F 1 "LED" V 7298 3532 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7350 3650 50  0001 C CNN
+F 3 "~" H 7350 3650 50  0001 C CNN
+	1    7350 3650
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
+	6450 3500 6450 3450
+Wire Wire Line
+	6750 3450 6750 3500
+Wire Wire Line
+	7050 3500 7050 3450
+Wire Wire Line
+	7350 3450 7350 3500
+Wire Wire Line
+	6450 3100 6450 3150
+Wire Wire Line
+	6750 3150 6750 3100
+Wire Wire Line
+	7050 3150 7050 3100
+Wire Wire Line
+	7350 3150 7350 3100
+$Comp
+L Device:LED D50
+U 1 1 606ABEDD
+P 6450 4000
+F 0 "D50" V 6489 3882 50  0000 R CNN
+F 1 "LED" V 6398 3882 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6450 4000 50  0001 C CNN
+F 3 "~" H 6450 4000 50  0001 C CNN
+	1    6450 4000
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D51
+U 1 1 606AC0D7
+P 6750 4000
+F 0 "D51" V 6789 3882 50  0000 R CNN
+F 1 "LED" V 6698 3882 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6750 4000 50  0001 C CNN
+F 3 "~" H 6750 4000 50  0001 C CNN
+	1    6750 4000
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D52
+U 1 1 606AC0E1
+P 7050 4000
+F 0 "D52" V 7089 3882 50  0000 R CNN
+F 1 "LED" V 6998 3882 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7050 4000 50  0001 C CNN
+F 3 "~" H 7050 4000 50  0001 C CNN
+	1    7050 4000
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D53
+U 1 1 606AC0EB
+P 7350 4000
+F 0 "D53" V 7389 3882 50  0000 R CNN
+F 1 "LED" V 7298 3882 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7350 4000 50  0001 C CNN
+F 3 "~" H 7350 4000 50  0001 C CNN
+	1    7350 4000
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D54
+U 1 1 606AC0F5
+P 6450 4350
+F 0 "D54" V 6489 4232 50  0000 R CNN
+F 1 "LED" V 6398 4232 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6450 4350 50  0001 C CNN
+F 3 "~" H 6450 4350 50  0001 C CNN
+	1    6450 4350
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D55
+U 1 1 606AC0FF
+P 6750 4350
+F 0 "D55" V 6789 4232 50  0000 R CNN
+F 1 "LED" V 6698 4232 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6750 4350 50  0001 C CNN
+F 3 "~" H 6750 4350 50  0001 C CNN
+	1    6750 4350
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D56
+U 1 1 606AC109
+P 7050 4350
+F 0 "D56" V 7089 4232 50  0000 R CNN
+F 1 "LED" V 6998 4232 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7050 4350 50  0001 C CNN
+F 3 "~" H 7050 4350 50  0001 C CNN
+	1    7050 4350
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D57
+U 1 1 606AC113
+P 7350 4350
+F 0 "D57" V 7389 4232 50  0000 R CNN
+F 1 "LED" V 7298 4232 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7350 4350 50  0001 C CNN
+F 3 "~" H 7350 4350 50  0001 C CNN
+	1    7350 4350
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
+	6450 4200 6450 4150
+Wire Wire Line
+	6750 4150 6750 4200
+Wire Wire Line
+	7050 4200 7050 4150
+Wire Wire Line
+	7350 4150 7350 4200
+$Comp
+L Device:LED D58
+U 1 1 606AC121
+P 6450 4700
+F 0 "D58" V 6489 4582 50  0000 R CNN
+F 1 "LED" V 6398 4582 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6450 4700 50  0001 C CNN
+F 3 "~" H 6450 4700 50  0001 C CNN
+	1    6450 4700
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D59
+U 1 1 606AC12B
+P 6750 4700
+F 0 "D59" V 6789 4582 50  0000 R CNN
+F 1 "LED" V 6698 4582 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6750 4700 50  0001 C CNN
+F 3 "~" H 6750 4700 50  0001 C CNN
+	1    6750 4700
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D60
+U 1 1 606AC135
+P 7050 4700
+F 0 "D60" V 7089 4582 50  0000 R CNN
+F 1 "LED" V 6998 4582 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7050 4700 50  0001 C CNN
+F 3 "~" H 7050 4700 50  0001 C CNN
+	1    7050 4700
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D61
+U 1 1 606AC13F
+P 7350 4700
+F 0 "D61" V 7389 4582 50  0000 R CNN
+F 1 "LED" V 7298 4582 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7350 4700 50  0001 C CNN
+F 3 "~" H 7350 4700 50  0001 C CNN
+	1    7350 4700
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D62
+U 1 1 606AC149
+P 6450 5050
+F 0 "D62" V 6489 4932 50  0000 R CNN
+F 1 "LED" V 6398 4932 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6450 5050 50  0001 C CNN
+F 3 "~" H 6450 5050 50  0001 C CNN
+	1    6450 5050
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D63
+U 1 1 606AC153
+P 6750 5050
+F 0 "D63" V 6789 4932 50  0000 R CNN
+F 1 "LED" V 6698 4932 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 6750 5050 50  0001 C CNN
+F 3 "~" H 6750 5050 50  0001 C CNN
+	1    6750 5050
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D64
+U 1 1 606AC15D
+P 7050 5050
+F 0 "D64" V 7089 4932 50  0000 R CNN
+F 1 "LED" V 6998 4932 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7050 5050 50  0001 C CNN
+F 3 "~" H 7050 5050 50  0001 C CNN
+	1    7050 5050
+	0    -1   -1   0   
+$EndComp
+$Comp
+L Device:LED D65
+U 1 1 606AC167
+P 7350 5050
+F 0 "D65" V 7389 4932 50  0000 R CNN
+F 1 "LED" V 7298 4932 50  0000 R CNN
+F 2 "LED_SMD:LED_PLCC_2835" H 7350 5050 50  0001 C CNN
+F 3 "~" H 7350 5050 50  0001 C CNN
+	1    7350 5050
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
+	6450 4900 6450 4850
+Wire Wire Line
+	6750 4850 6750 4900
+Wire Wire Line
+	7050 4900 7050 4850
+Wire Wire Line
+	7350 4850 7350 4900
+Wire Wire Line
+	6450 4500 6450 4550
+Wire Wire Line
+	6750 4550 6750 4500
+Wire Wire Line
+	7050 4550 7050 4500
+Wire Wire Line
+	7350 4550 7350 4500
+Wire Wire Line
+	6450 3800 6450 3850
+Wire Wire Line
+	6750 3850 6750 3800
+Wire Wire Line
+	7050 3850 7050 3800
+Wire Wire Line
+	7350 3850 7350 3800
+Wire Wire Line
+	6450 5200 6450 5350
+Wire Wire Line
+	4600 5350 4600 3100
+Wire Wire Line
+	4600 3100 3850 3100
+Wire Wire Line
+	3850 3200 4500 3200
+Wire Wire Line
+	4500 3200 4500 5450
+Wire Wire Line
+	6750 5450 6750 5200
+Wire Wire Line
+	7050 5200 7050 5550
+Wire Wire Line
+	4400 5550 4400 3300
+Wire Wire Line
+	4400 3300 3850 3300
+Wire Wire Line
+	3850 3400 4300 3400
+Wire Wire Line
+	4300 3400 4300 5650
+Wire Wire Line
+	7350 5650 7350 5200
+Wire Wire Line
+	1500 3100 2900 3100
+Wire Wire Line
+	4600 5350 6450 5350
+Wire Wire Line
+	4500 5450 6750 5450
+Wire Wire Line
+	4400 5550 7050 5550
+Wire Wire Line
+	4300 5650 7350 5650
+Text Notes 7700 2650 0    50   ~ 0
+LEDs: L128-4095HA3500001\nVf: 3V\nIf: ~~60 mA
+Text Notes 5550 2250 0    50   ~ 0
+V  = ~~ 24V
+Text Notes 5550 2350 0    50   ~ 0
+I = ~~300 mA
+$Comp
+L Device:CP C52
+U 1 1 6067BB94
+P 5100 2050
+F 0 "C52" H 4982 2004 50  0000 R CNN
+F 1 "EEEFK1H390SP 39u/50V" H 4982 2095 50  0000 R CNN
+F 2 "Capacitor_SMD:CP_Elec_6.3x5.8" H 5138 1900 50  0001 C CNN
+F 3 "~" H 5100 2050 50  0001 C CNN
+	1    5100 2050
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	5100 2200 5100 2400
+Connection ~ 5100 2400
+Wire Wire Line
+	5100 2400 5250 2400
+Wire Wire Line
+	5100 1900 4400 1900
+Wire Wire Line
+	4400 1900 4400 2600
+$Comp
+L power:GND #PWR0136
+U 1 1 6068937B
+P 4400 2600
+F 0 "#PWR0136" H 4400 2350 50  0001 C CNN
+F 1 "GND" H 4405 2427 50  0000 C CNN
+F 2 "" H 4400 2600 50  0001 C CNN
+F 3 "" H 4400 2600 50  0001 C CNN
+	1    4400 2600
+	1    0    0    -1  
+$EndComp
+Text Label 6100 2400 0    50   ~ 0
+LED_SUPPLY
+$Comp
+L Connector:TestPoint TP4
+U 1 1 60640D50
+P 6450 2000
+F 0 "TP4" H 6508 2118 50  0000 L CNN
+F 1 "LED_SUPPLY" H 6508 2027 50  0000 L CNN
+F 2 "TestPoint:TestPoint_Pad_D1.5mm" H 6650 2000 50  0001 C CNN
+F 3 "~" H 6650 2000 50  0001 C CNN
+	1    6450 2000
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	6450 2000 6450 2400
+Text Notes 3250 2100 0    50   ~ 0
+22 uH
+Text Notes 2150 4650 0    50   ~ 0
+Max Current = 60 mA\nYou may use 27k for 88mA. This turned out to be fine.
+Text Notes 850  3900 0    50   ~ 0
+f = 1.08 MHz
+Text Notes 1650 1850 0    50   ~ 0
+For the calculation of the component values see 'lp8867-calc.py'
+Text Notes 6050 2800 0    50   ~ 0
+(15pF)
+$EndSCHEMATC

pcb/generate-led-coords.py

@@ -2,10 +2,10 @@
 import numpy as np
 import pandas as pd
 
-led_count = 30
-ring_diameter = 74
+led_count = 32
+ring_diameter = 93
 hole_center_coords = (70, 70)
-led_footprint_rotation = 180
+led_footprint_rotation = 90
 
 df = pd.DataFrame({'x': [], 'y': [], 'angle': []})
 pd.set_option('display.float_format', lambda x: '%.3f' % x)
@@ -16,4 +16,4 @@ for led in range(led_count):
     y_coord = -np.sin(led_angle) * ring_diameter / 2 + hole_center_coords[1]
     df = df.append({'x': x_coord, 'y':y_coord, 'angle': (led_angle / np.pi * 180 + led_footprint_rotation) % 360}, ignore_index=True)
 
-print(df)
+print(df)

pcb/lp8867-calc.py

@@ -0,0 +1,100 @@
+#!/bin/python
+
+import numpy as np
+import eseries as es
+
+def calc_fsw_from_r_fset(r_fset):
+    fsw = 67600 / (r_fset / 1e3 + 6.4)
+    fsw = fsw * 1e3
+    return fsw
+
+def calc_r_fset_from_fsw(fsw):
+    fsw = fsw / 1e3
+    r = 67600 / (fsw) - 6.4
+    r = r * 1e3
+    return r
+
+def calc_r_iset_from_i(i):
+    i = i * 1e3
+    r = 2000 * 1.2 / i
+    r = r * 1e3
+    return r
+def calc_i_from_r_iset(r):
+    r = r * 1e-3
+    i = 2000 * 1.2 / r
+    i = i * 1e-3
+    return i
+
+def calc_vout(r1, r2, k):
+    r1 = r1 / 1000
+    r2 = r2 / 1000
+    v = (1.2 / r2 + k * 0.0387) * r1 + 1.2
+    return v
+
+switching_freq = 1.1e6
+output_voltage_nom = 24 + 0.9
+inductor_value = 22e-6
+input_voltage = 12
+output_current_per_lane = 110e-3
+desired_e_series = es.E12
+r1 = 560e3
+r2 = 100e3
+
+# Calculate the parameters
+print('Calculating for the given parameters:')
+print(f'{switching_freq = }')
+print(f'{output_voltage_nom = } and {input_voltage = }')
+print(f'{inductor_value =}')
+print(f'{desired_e_series = }')
+print('')
+
+rfset = calc_r_fset_from_fsw(switching_freq)
+print(f'{rfset = }')
+
+# Find the nearest value in the e series
+rfset = es.find_nearest(desired_e_series, rfset)
+f_sw = calc_fsw_from_r_fset(rfset)
+
+print(f'The nearest value from the E series is: {rfset = }')
+freq_error = (f_sw - switching_freq) / switching_freq * 100
+print(f'Resulting switching frequency is {f_sw} (Error: {freq_error:.1f} %)')
+
+print(f"Desired output current per lane is {output_current_per_lane} A")
+r_iset = calc_r_iset_from_i(output_current_per_lane)
+print(f'Resulting in {r_iset = }')
+r_iset = es.find_nearest(desired_e_series, r_iset)
+output_current_per_lane = calc_i_from_r_iset(r_iset)
+print(f'Nearest e series value {r_iset = } resulting in an LED current of {output_current_per_lane} A')
+
+d = (output_voltage_nom - input_voltage) / output_voltage_nom
+d_inv = 1-d
+print(f"Expected duty cycle: {d}")
+i_ripple = (output_voltage_nom- input_voltage) / (2 * inductor_value * f_sw) * (input_voltage / output_voltage_nom)
+print(f'Ripple current: {i_ripple} A')
+i_sat_min = output_current_per_lane * 4 / d_inv + i_ripple
+print(f'Minimum saturation current of inductor: {i_sat_min:.3f} A')
+
+print(f'Voltage divider {r1 = } | {r2 = }')
+print(f'Output voltage initial: {calc_vout(r1, r2, 0.88)} V')
+print(f'Output voltage maximum: {calc_vout(r1, r2, 1)} V')
+print(f'Output voltage minimum: {calc_vout(r1, r2, 0)} V')
+
+ovp = output_voltage_nom + (r1/r2 + 1)*(2.3 - 1.2)
+
+print(f'Over voltage protection: {ovp} V')
+
+ratio = r1/r2
+print(f'Resistance ratio is {ratio}')
+if f_sw <= 1150e3:
+    ratio_range = (5, 10)
+else:
+    ratio_range = (10, 20)
+
+if ratio < ratio_range[0] or ratio > ratio_range[1]:
+    print('Ratio is outside recommended limits!')
+else:
+    print('Resistance ratio is inside recommended limits')
+
+# Loop stability
+cfb = 1 / (2 * np.pi * 20e3 * r1 )
+print(f'Loop stability capacitor value: {cfb} F')

pcb/microscope-ring-light-cache.lib

@@ -24,6 +24,23 @@ X Pin_4 4 -200 -200 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
+# Connector_TestPoint
+#
+DEF Connector_TestPoint TP 0 30 N N 1 F N
+F0 "TP" 0 270 50 H V C CNN
+F1 "Connector_TestPoint" 0 200 50 H V C CNN
+F2 "" 200 0 50 H I C CNN
+F3 "" 200 0 50 H I C CNN
+$FPLIST
+ Pin*
+ Test*
+$ENDFPLIST
+DRAW
+C 0 130 30 0 1 0 N
+X 1 1 0 0 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
 # Device_C
 #
 DEF Device_C C 0 10 N Y 1 F N
@@ -83,24 +100,48 @@ X 2 2 150 0 50 L 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
-# Device_Jumper_NO_Small
+# Device_D_Schottky
 #
-DEF Device_Jumper_NO_Small JP 0 30 N N 1 F N
-F0 "JP" 0 80 50 H V C CNN
-F1 "Device_Jumper_NO_Small" 10 -60 50 H V C CNN
+DEF Device_D_Schottky D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "Device_D_Schottky" 0 -100 50 H V C CNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 $FPLIST
- SolderJumper*Open*
- Jumper*
- TestPoint*2Pads*
- TestPoint*Bridge*
+ TO-???*
+ *_Diode_*
+ *SingleDiode*
+ D_*
 $ENDFPLIST
 DRAW
-C -40 0 20 0 1 0 N
-C 40 0 20 0 1 0 N
-X 1 1 -100 0 40 R 50 50 0 1 P
-X 2 2 100 0 40 L 50 50 0 1 P
+P 2 0 1 0 50 0 -50 0 N
+P 4 0 1 10 50 50 50 -50 -50 0 50 50 N
+P 6 0 1 10 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N
+X K 1 -150 0 100 R 50 50 1 1 P
+X A 2 150 0 100 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# Device_LED
+#
+DEF Device_LED D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "Device_LED" 0 -100 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+$FPLIST
+ LED*
+ LED_SMD:*
+ LED_THT:*
+$ENDFPLIST
+DRAW
+P 2 0 1 10 -50 -50 -50 50 N
+P 2 0 1 0 -50 0 50 0 N
+P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
+P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
+P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
+X K 1 -150 0 100 R 50 50 1 1 P
+X A 2 150 0 100 L 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
@@ -156,44 +197,6 @@ X ~ 2 0 -150 50 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
-# Device_Rotary_Encoder_Switch
-#
-DEF Device_Rotary_Encoder_Switch SW 0 10 Y N 1 F N
-F0 "SW" 0 260 50 H V C CNN
-F1 "Device_Rotary_Encoder_Switch" 0 -260 50 H V C CNN
-F2 "" -150 160 50 H I C CNN
-F3 "" 0 260 50 H I C CNN
-$FPLIST
- RotaryEncoder*Switch*
-$ENDFPLIST
-DRAW
-A -15 -2 108 -899 899 0 1 10 N -15 -110 -15 105
-C -150 0 10 0 1 0 F
-C -15 0 75 0 1 10 N
-C 170 -40 5 0 1 10 N
-C 170 40 5 0 1 10 N
-S -200 200 200 -200 0 1 10 f
-P 2 0 1 10 -25 -70 -25 70 N
-P 2 0 1 10 -15 -70 -15 70 N
-P 2 0 1 10 -5 70 -5 -70 N
-P 2 0 1 10 150 0 135 0 N
-P 2 0 1 10 150 40 150 -40 N
-P 3 0 1 0 -200 -100 -150 -100 -150 -80 N
-P 3 0 1 0 -200 100 -150 100 -150 80 N
-P 3 0 1 10 10 -120 -20 -110 5 -95 N
-P 3 0 1 10 10 115 -20 105 5 90 N
-P 3 0 1 10 200 -100 170 -100 170 -40 N
-P 3 0 1 10 200 100 170 100 170 40 N
-P 4 0 1 0 -200 0 -150 0 -150 -40 -130 -80 N
-P 4 0 1 0 -170 0 -150 0 -150 40 -130 80 N
-X A A -300 100 100 R 50 50 1 1 P
-X B B -300 -100 100 R 50 50 1 1 P
-X C C -300 0 100 R 50 50 1 1 P
-X S1 S1 300 100 100 L 50 50 1 1 P
-X S2 S2 300 -100 100 L 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
 # LED_SK6812
 #
 DEF LED_SK6812 D 0 10 Y Y 1 F N
@@ -256,18 +259,19 @@ X PA3 9 500 200 100 L 50 50 1 1 B
 ENDDRAW
 ENDDEF
 #
-# Mechanical_MountingHole
+# Mechanical_MountingHole_Pad
 #
-DEF Mechanical_MountingHole H 0 40 Y Y 1 F N
-F0 "H" 0 200 50 H V C CNN
-F1 "Mechanical_MountingHole" 0 125 50 H V C CNN
+DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
+F0 "H" 0 250 50 H V C CNN
+F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 $FPLIST
- MountingHole*
+ MountingHole*Pad*
 $ENDFPLIST
 DRAW
-C 0 0 50 0 1 50 N
+C 0 50 50 0 1 50 N
+X 1 1 0 -100 100 U 50 50 1 1 I
 ENDDRAW
 ENDDEF
 #
@@ -413,6 +417,45 @@ X TX/~TRST 9 100 -950 100 L 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
+# shimatta_connectors_Rotary_Encoder_Switch_Mounting
+#
+DEF shimatta_connectors_Rotary_Encoder_Switch_Mounting SW 0 10 Y N 1 F N
+F0 "SW" 0 260 50 H V C CNN
+F1 "shimatta_connectors_Rotary_Encoder_Switch_Mounting" 0 -260 50 H V C CNN
+F2 "" -150 160 50 H I C CNN
+F3 "" 0 260 50 H I C CNN
+$FPLIST
+ RotaryEncoder*Switch*
+$ENDFPLIST
+DRAW
+A -15 -2 108 -899 899 0 1 10 N -15 -110 -15 105
+C -150 0 10 0 1 0 F
+C -15 0 75 0 1 10 N
+C 170 -40 5 0 1 10 N
+C 170 40 5 0 1 10 N
+S -200 200 200 -200 0 1 10 f
+P 2 0 1 10 -25 -70 -25 70 N
+P 2 0 1 10 -15 -70 -15 70 N
+P 2 0 1 10 -5 70 -5 -70 N
+P 2 0 1 10 150 0 135 0 N
+P 2 0 1 10 150 40 150 -40 N
+P 3 0 1 0 -200 -100 -150 -100 -150 -80 N
+P 3 0 1 0 -200 100 -150 100 -150 80 N
+P 3 0 1 10 10 -120 -20 -110 5 -95 N
+P 3 0 1 10 10 115 -20 105 5 90 N
+P 3 0 1 10 200 -100 170 -100 170 -40 N
+P 3 0 1 10 200 100 170 100 170 40 N
+P 4 0 1 0 -200 0 -150 0 -150 -40 -130 -80 N
+P 4 0 1 0 -170 0 -150 0 -150 40 -130 80 N
+X A A -300 100 100 R 50 50 1 1 P
+X B B -300 -100 100 R 50 50 1 1 P
+X C C -300 0 100 R 50 50 1 1 P
+X MP MP 0 -300 100 U 50 50 1 1 P
+X S1 S1 300 100 100 L 50 50 1 1 P
+X S2 S2 300 -100 100 L 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
 # shimatta_interface_ST3485E
 #
 DEF shimatta_interface_ST3485E U 0 40 Y Y 1 F N
@@ -453,4 +496,37 @@ X VCC 5 100 100 100 D 50 50 2 1 W
 ENDDRAW
 ENDDEF
 #
+# shimatta_regulators_LP8867
+#
+DEF shimatta_regulators_LP8867 U 0 40 Y Y 1 F N
+F0 "U" 50 50 50 H V C CNN
+F1 "shimatta_regulators_LP8867" 250 50 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+S 0 0 750 -1300 0 1 0 f
+X VIN 1 -100 -100 100 R 50 50 1 1 W
+X ISET 10 -100 -850 100 R 50 50 1 1 B
+X GND 11 300 -1400 100 U 50 50 1 1 W
+X OUT4 12 850 -750 100 L 50 50 1 1 C
+X OUT3 13 850 -650 100 L 50 50 1 1 C
+X OUT2 14 850 -550 100 L 50 50 1 1 C
+X OUT1 15 850 -450 100 L 50 50 1 1 C
+X FB 16 850 -200 100 L 50 50 1 1 I
+X PGND 17 600 -1400 100 U 50 50 1 1 W
+X SW 18 850 -100 100 L 50 50 1 1 w
+X NC 19 -100 -1200 100 R 50 50 1 1 N
+X LDO 2 -100 -950 100 R 50 50 1 1 w
+X VIN 20 -100 -200 100 R 50 50 1 1 W
+X GNDPAD 21 400 -1400 100 U 50 50 1 1 W
+X FSET 3 -100 -450 100 R 50 50 1 1 B
+X VDDIO/EN 4 -100 -350 100 R 50 50 1 1 W
+X FAULT 5 -100 -550 100 R 50 50 1 1 C V
+X SYNC 6 -100 -650 100 R 50 50 1 1 I
+X PWM 7 -100 -750 100 R 50 50 1 1 I
+X NC 8 -100 -1100 100 R 50 50 1 1 N
+X GND 9 500 -1400 100 U 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
 #End Library

pcb/microscope-ring-light.pro

@@ -1,4 +1,4 @@
-update=Sun 24 Jan 2021 03:48:54 PM CET
+update=Fri 09 Apr 2021 10:42:17 PM CEST
 version=1
 last_client=kicad
 [general]
@@ -16,14 +16,14 @@ LibDir=
 version=1
 PageLayoutDescrFile=
 LastNetListRead=
-CopperLayerCount=2
+CopperLayerCount=4
 BoardThickness=1.6
 AllowMicroVias=0
 AllowBlindVias=0
 RequireCourtyardDefinitions=0
 ProhibitOverlappingCourtyards=1
-MinTrackWidth=0.2
-MinViaDiameter=0.4
+MinTrackWidth=0.25
+MinViaDiameter=0.5
 MinViaDrill=0.3
 MinMicroViaDiameter=0.2
 MinMicroViaDrill=0.09999999999999999
@@ -35,12 +35,12 @@ TrackWidth4=0.8
 TrackWidth5=2.5
 ViaDiameter1=0.8
 ViaDrill1=0.4
-ViaDiameter2=0.5
+ViaDiameter2=0.6
 ViaDrill2=0.3
 ViaDiameter3=0.9
 ViaDrill3=0.5
-dPairWidth1=0.2
-dPairGap1=0.25
+dPairWidth1=0.3
+dPairGap1=0.26
 dPairViaGap1=0.25
 SilkLineWidth=0.12
 SilkTextSizeV=1
@@ -72,12 +72,12 @@ Type=0
 Enabled=1
 [pcbnew/Layer.In1.Cu]
 Name=In1.Cu
-Type=0
-Enabled=0
+Type=1
+Enabled=1
 [pcbnew/Layer.In2.Cu]
 Name=In2.Cu
-Type=0
-Enabled=0
+Type=1
+Enabled=1
 [pcbnew/Layer.In3.Cu]
 Name=In3.Cu
 Type=0
@@ -241,6 +241,38 @@ ViaDiameter=0.8
 ViaDrill=0.4
 uViaDiameter=0.3
 uViaDrill=0.1
-dPairWidth=0.2
+dPairWidth=0.3
+dPairGap=0.26
+dPairViaGap=0.25
+[pcbnew/Netclasses/1]
+Name=DMX-DIFF120
+Clearance=0.2
+TrackWidth=0.25
+ViaDiameter=0.6
+ViaDrill=0.3
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.25
+dPairGap=0.3
+dPairViaGap=0.25
+[pcbnew/Netclasses/2]
+Name=LED_SUPPLY
+Clearance=0.35
+TrackWidth=0.25
+ViaDiameter=0.8
+ViaDrill=0.4
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.3
 dPairGap=0.25
 dPairViaGap=0.25
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1

pcb/microscope-ring-light.sch

@@ -3,10 +3,10 @@ EELAYER 30 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
-Sheet 1 2
+Sheet 1 3
 Title "Microscope LED Ring Light"
-Date ""
-Rev "v1.0"
+Date "2021-04-06"
+Rev "v2.1"
 Comp "Shimatta"
 Comment1 ""
 Comment2 ""
@@ -26,10 +26,10 @@ F 4 "STM32F030F4P6" H 4500 4350 50  0001 C CNN "TME Part Number"
 	1    0    0    -1  
 $EndComp
 $Comp
-L Device:R R7
+L Device:R R4
 U 1 1 5FFD01D5
 P 3000 3600
-F 0 "R7" H 3070 3646 50  0000 L CNN
+F 0 "R4" H 3070 3646 50  0000 L CNN
 F 1 "10k" H 3070 3555 50  0000 L CNN
 F 2 "Resistor_SMD:R_0603_1608Metric" V 2930 3600 50  0001 C CNN
 F 3 "~" H 3000 3600 50  0001 C CNN
@@ -41,10 +41,10 @@ Wire Wire Line
 Wire Wire Line
 	2000 4000 2000 3900
 $Comp
-L power:+3V3 #PWR024
+L power:+3V3 #PWR021
 U 1 1 5FFD26BA
 P 2000 3900
-F 0 "#PWR024" H 2000 3750 50  0001 C CNN
+F 0 "#PWR021" H 2000 3750 50  0001 C CNN
 F 1 "+3V3" H 2015 4073 50  0000 C CNN
 F 2 "" H 2000 3900 50  0001 C CNN
 F 3 "" H 2000 3900 50  0001 C CNN
@@ -87,76 +87,32 @@ Wire Wire Line
 Wire Wire Line
 	3000 3450 3000 3400
 $Comp
-L power:+3V3 #PWR022
+L power:+3V3 #PWR019
 U 1 1 5FFD89F4
 P 3000 3400
-F 0 "#PWR022" H 3000 3250 50  0001 C CNN
+F 0 "#PWR019" H 3000 3250 50  0001 C CNN
 F 1 "+3V3" H 3015 3573 50  0000 C CNN
 F 2 "" H 3000 3400 50  0001 C CNN
 F 3 "" H 3000 3400 50  0001 C CNN
 	1    3000 3400
 	1    0    0    -1  
 $EndComp
-Wire Wire Line
-	4000 4050 2600 4050
 $Comp
-L Device:Jumper_NO_Small JP1
-U 1 1 5FFD9E07
-P 2600 3600
-F 0 "JP1" V 2646 3552 50  0000 R CNN
-F 1 "BOOT0" V 2555 3552 50  0000 R CNN
-F 2 "Jumper:SolderJumper-2_P1.3mm_Open_RoundedPad1.0x1.5mm" H 2600 3600 50  0001 C CNN
-F 3 "~" H 2600 3600 50  0001 C CNN
-	1    2600 3600
-	0    -1   -1   0   
-$EndComp
-Connection ~ 2600 4050
-$Comp
-L power:+3V3 #PWR021
-U 1 1 5FFDBC4C
-P 2600 3400
-F 0 "#PWR021" H 2600 3250 50  0001 C CNN
-F 1 "+3V3" H 2615 3573 50  0000 C CNN
-F 2 "" H 2600 3400 50  0001 C CNN
-F 3 "" H 2600 3400 50  0001 C CNN
-	1    2600 3400
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	2600 4050 2600 4100
-$Comp
-L Device:R R8
+L Device:R R5
 U 1 1 5FFDCED5
-P 2600 4300
-F 0 "R8" H 2670 4346 50  0000 L CNN
-F 1 "10k" H 2670 4255 50  0000 L CNN
-F 2 "Resistor_SMD:R_0603_1608Metric" V 2530 4300 50  0001 C CNN
-F 3 "~" H 2600 4300 50  0001 C CNN
-	1    2600 4300
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	2600 3500 2600 3400
-Wire Wire Line
-	2600 3700 2600 4050
-Wire Wire Line
-	2600 4450 2600 5350
-$Comp
-L power:GND #PWR027
-U 1 1 5FFE683B
-P 2600 5350
-F 0 "#PWR027" H 2600 5100 50  0001 C CNN
-F 1 "GND" H 2605 5177 50  0000 C CNN
-F 2 "" H 2600 5350 50  0001 C CNN
-F 3 "" H 2600 5350 50  0001 C CNN
-	1    2600 5350
-	1    0    0    -1  
+P 3250 4050
+F 0 "R5" H 3320 4096 50  0000 L CNN
+F 1 "10k" H 3320 4005 50  0000 L CNN
+F 2 "Resistor_SMD:R_0603_1608Metric" V 3180 4050 50  0001 C CNN
+F 3 "~" H 3250 4050 50  0001 C CNN
+	1    3250 4050
+	0    1    1    0   
 $EndComp
 $Comp
-L power:GND #PWR030
+L power:GND #PWR029
 U 1 1 5FFE7BEF
 P 4500 5350
-F 0 "#PWR030" H 4500 5100 50  0001 C CNN
+F 0 "#PWR029" H 4500 5100 50  0001 C CNN
 F 1 "GND" H 4505 5177 50  0000 C CNN
 F 2 "" H 4500 5350 50  0001 C CNN
 F 3 "" H 4500 5350 50  0001 C CNN
@@ -175,10 +131,10 @@ Wire Wire Line
 	4500 3550 4500 3400
 Connection ~ 4500 3550
 $Comp
-L power:+3V3 #PWR023
+L power:+3V3 #PWR020
 U 1 1 5FFEC449
 P 4500 3400
-F 0 "#PWR023" H 4500 3250 50  0001 C CNN
+F 0 "#PWR020" H 4500 3250 50  0001 C CNN
 F 1 "+3V3" H 4515 3573 50  0000 C CNN
 F 2 "" H 4500 3400 50  0001 C CNN
 F 3 "" H 4500 3400 50  0001 C CNN
@@ -207,11 +163,6 @@ F 3 "" H 1400 3950 50  0001 C CNN
 	1    1400 3950
 	1    0    0    -1  
 $EndComp
-Wire Wire Line
-	1500 4100 2600 4100
-Connection ~ 2600 4100
-Wire Wire Line
-	2600 4100 2600 4150
 $Comp
 L Device:Crystal Y1
 U 1 1 5FFF8B8B
@@ -224,17 +175,6 @@ F 3 "~" H 3150 4700 50  0001 C CNN
 	0    1    1    0   
 $EndComp
 $Comp
-L Device:R R9
-U 1 1 5FFFA551
-P 3750 4750
-F 0 "R9" V 3543 4750 50  0000 C CNN
-F 1 "0" V 3634 4750 50  0000 C CNN
-F 2 "Resistor_SMD:R_0603_1608Metric" V 3680 4750 50  0001 C CNN
-F 3 "~" H 3750 4750 50  0001 C CNN
-	1    3750 4750
-	0    1    1    0   
-$EndComp
-$Comp
 L Device:C C14
 U 1 1 5FFFC481
 P 650 5500
@@ -294,10 +234,10 @@ Wire Wire Line
 Wire Wire Line
 	1100 5700 1100 5750
 $Comp
-L power:GND #PWR031
+L power:GND #PWR030
 U 1 1 600029C8
 P 1100 5750
-F 0 "#PWR031" H 1100 5500 50  0001 C CNN
+F 0 "#PWR030" H 1100 5500 50  0001 C CNN
 F 1 "GND" H 1105 5577 50  0000 C CNN
 F 2 "" H 1100 5750 50  0001 C CNN
 F 3 "" H 1100 5750 50  0001 C CNN
@@ -314,10 +254,6 @@ Wire Wire Line
 	3900 4500 3900 4650
 Wire Wire Line
 	3900 4650 4000 4650
-Wire Wire Line
-	3900 4750 4000 4750
-Wire Wire Line
-	3600 4750 3550 4750
 Wire Wire Line
 	3550 4750 3550 4900
 Wire Wire Line
@@ -357,10 +293,10 @@ Wire Wire Line
 Wire Wire Line
 	3150 5250 3150 5350
 $Comp
-L power:GND #PWR028
+L power:GND #PWR027
 U 1 1 60022275
 P 2800 5350
-F 0 "#PWR028" H 2800 5100 50  0001 C CNN
+F 0 "#PWR027" H 2800 5100 50  0001 C CNN
 F 1 "GND" H 2805 5177 50  0000 C CNN
 F 2 "" H 2800 5350 50  0001 C CNN
 F 3 "" H 2800 5350 50  0001 C CNN
@@ -368,26 +304,18 @@ F 3 "" H 2800 5350 50  0001 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L power:GND #PWR029
+L power:GND #PWR028
 U 1 1 60022617
 P 3150 5350
-F 0 "#PWR029" H 3150 5100 50  0001 C CNN
+F 0 "#PWR028" H 3150 5100 50  0001 C CNN
 F 1 "GND" H 3155 5177 50  0000 C CNN
 F 2 "" H 3150 5350 50  0001 C CNN
 F 3 "" H 3150 5350 50  0001 C CNN
 	1    3150 5350
 	1    0    0    -1  
 $EndComp
-Wire Wire Line
-	1500 4900 1850 4900
-Wire Wire Line
-	1850 4800 1500 4800
 Text Label 3700 3850 0    50   ~ 0
 ~RESET
-Text Label 1850 4800 2    50   ~ 0
-STM_TX
-Text Label 1850 4900 2    50   ~ 0
-STM_RX
 Text Label 5500 4650 2    50   ~ 0
 STM_TX
 Text Label 5500 4750 2    50   ~ 0
@@ -408,10 +336,10 @@ F 3 "https://www.st.com/resource/en/datasheet/st3485ec.pdf" H 3950 1300 50  0001
 	-1   0    0    -1  
 $EndComp
 $Comp
-L power:GND #PWR012
+L power:GND #PWR06
 U 1 1 60084ADE
 P 1000 1500
-F 0 "#PWR012" H 1000 1250 50  0001 C CNN
+F 0 "#PWR06" H 1000 1250 50  0001 C CNN
 F 1 "GND" H 1005 1327 50  0000 C CNN
 F 2 "" H 1000 1500 50  0001 C CNN
 F 3 "" H 1000 1500 50  0001 C CNN
@@ -446,10 +374,10 @@ Wire Wire Line
 Wire Wire Line
 	3050 1800 3050 2300
 $Comp
-L power:GND #PWR016
+L power:GND #PWR015
 U 1 1 600910D2
 P 3050 2300
-F 0 "#PWR016" H 3050 2050 50  0001 C CNN
+F 0 "#PWR015" H 3050 2050 50  0001 C CNN
 F 1 "GND" H 3055 2127 50  0000 C CNN
 F 2 "" H 3050 2300 50  0001 C CNN
 F 3 "" H 3050 2300 50  0001 C CNN
@@ -462,62 +390,16 @@ Wire Wire Line
 	4950 1800 4050 1800
 Text Label 4950 1400 2    50   ~ 0
 STM_RX
-$Comp
-L Device:R R2
-U 1 1 60097820
-P 4300 1400
-F 0 "R2" V 4093 1400 50  0000 C CNN
-F 1 "22" V 4184 1400 50  0000 C CNN
-F 2 "Resistor_SMD:R_0603_1608Metric" V 4230 1400 50  0001 C CNN
-F 3 "~" H 4300 1400 50  0001 C CNN
-	1    4300 1400
-	0    1    1    0   
-$EndComp
-Wire Wire Line
-	4050 1400 4150 1400
-Wire Wire Line
-	4450 1400 4950 1400
-Wire Wire Line
-	4050 1500 4100 1500
-Wire Wire Line
-	4100 1500 4100 1150
-Connection ~ 4100 1500
-Wire Wire Line
-	4100 1500 4950 1500
-$Comp
-L Device:R R1
-U 1 1 600A136C
-P 4100 1000
-F 0 "R1" H 4030 954 50  0000 R CNN
-F 1 "10k" H 4030 1045 50  0000 R CNN
-F 2 "Resistor_SMD:R_0603_1608Metric" V 4030 1000 50  0001 C CNN
-F 3 "~" H 4100 1000 50  0001 C CNN
-	1    4100 1000
-	-1   0    0    1   
-$EndComp
-$Comp
-L power:+3V3 #PWR02
-U 1 1 600A4832
-P 4100 700
-F 0 "#PWR02" H 4100 550 50  0001 C CNN
-F 1 "+3V3" H 4115 873 50  0000 C CNN
-F 2 "" H 4100 700 50  0001 C CNN
-F 3 "" H 4100 700 50  0001 C CNN
-	1    4100 700 
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4100 700  4100 850 
 Wire Wire Line
 	3050 800  2700 800 
 Connection ~ 3050 800 
 Wire Wire Line
 	3050 800  3050 700 
 $Comp
-L power:GND #PWR06
+L power:GND #PWR05
 U 1 1 600A8C1F
 P 2700 1300
-F 0 "#PWR06" H 2700 1050 50  0001 C CNN
+F 0 "#PWR05" H 2700 1050 50  0001 C CNN
 F 1 "GND" H 2705 1127 50  0000 C CNN
 F 2 "" H 2700 1300 50  0001 C CNN
 F 3 "" H 2700 1300 50  0001 C CNN
@@ -543,57 +425,13 @@ Text Label 2100 1650 0    50   ~ 0
 DMX+
 Text Label 2100 1950 0    50   ~ 0
 DMX-
-Wire Wire Line
-	4050 1700 4100 1700
-Text Label 4950 1700 2    50   ~ 0
-DMX_TXEN
 Text Label 4950 1500 2    50   ~ 0
-DMX_~RXEN
-Wire Wire Line
-	4100 1700 4100 1900
-Connection ~ 4100 1700
-Wire Wire Line
-	4100 1700 4950 1700
+DMX_~RX~TX
 $Comp
-L Device:R R5
-U 1 1 600BF70F
-P 4100 2050
-F 0 "R5" H 4030 2004 50  0000 R CNN
-F 1 "10k" H 4030 2095 50  0000 R CNN
-F 2 "Resistor_SMD:R_0603_1608Metric" V 4030 2050 50  0001 C CNN
-F 3 "~" H 4100 2050 50  0001 C CNN
-	1    4100 2050
-	-1   0    0    1   
-$EndComp
-$Comp
-L power:GND #PWR017
-U 1 1 600C2C2B
-P 4100 2300
-F 0 "#PWR017" H 4100 2050 50  0001 C CNN
-F 1 "GND" H 4105 2127 50  0000 C CNN
-F 2 "" H 4100 2300 50  0001 C CNN
-F 3 "" H 4100 2300 50  0001 C CNN
-	1    4100 2300
-	1    0    0    -1  
-$EndComp
-Wire Wire Line
-	4100 2300 4100 2200
-$Comp
-L Device:Rotary_Encoder_Switch SW1
-U 1 1 600CCA72
-P 2050 6550
-F 0 "SW1" H 2050 6917 50  0000 C CNN
-F 1 "Rotary_Encoder_Switch" H 2050 6826 50  0000 C CNN
-F 2 "shimatta_switch:EN11-VSM" H 1900 6710 50  0001 C CNN
-F 3 "~" H 2050 6810 50  0001 C CNN
-	1    2050 6550
-	1    0    0    -1  
-$EndComp
-$Comp
-L Device:R R4
+L Device:R R2
 U 1 1 600E065C
 P 1800 1800
-F 0 "R4" H 1870 1846 50  0000 L CNN
+F 0 "R2" H 1870 1846 50  0000 L CNN
 F 1 "120" H 1870 1755 50  0000 L CNN
 F 2 "Resistor_SMD:R_MiniMELF_MMA-0204" V 1730 1800 50  0001 C CNN
 F 3 "~" H 1800 1800 50  0001 C CNN
@@ -627,10 +465,10 @@ Wire Wire Line
 Wire Wire Line
 	1500 6550 1500 7300
 $Comp
-L power:GND #PWR034
+L power:GND #PWR033
 U 1 1 6010217D
 P 1500 7300
-F 0 "#PWR034" H 1500 7050 50  0001 C CNN
+F 0 "#PWR033" H 1500 7050 50  0001 C CNN
 F 1 "GND" H 1505 7127 50  0000 C CNN
 F 2 "" H 1500 7300 50  0001 C CNN
 F 3 "" H 1500 7300 50  0001 C CNN
@@ -641,8 +479,8 @@ $Comp
 L Device:C C17
 U 1 1 60102B69
 P 1100 6850
-F 0 "C17" H 1215 6896 50  0000 L CNN
-F 1 "100n" H 1215 6805 50  0000 L CNN
+F 0 "C17" H 850 6900 50  0000 L CNN
+F 1 "DNP" H 800 6800 50  0000 L CNN
 F 2 "Capacitor_SMD:C_0603_1608Metric" H 1138 6700 50  0001 C CNN
 F 3 "~" H 1100 6850 50  0001 C CNN
 	1    1100 6850
@@ -651,10 +489,10 @@ $EndComp
 Wire Wire Line
 	1100 7000 1100 7300
 $Comp
-L power:GND #PWR032
+L power:GND #PWR031
 U 1 1 6012A3A7
 P 1100 7300
-F 0 "#PWR032" H 1100 7050 50  0001 C CNN
+F 0 "#PWR031" H 1100 7050 50  0001 C CNN
 F 1 "GND" H 1105 7127 50  0000 C CNN
 F 2 "" H 1100 7300 50  0001 C CNN
 F 3 "" H 1100 7300 50  0001 C CNN
@@ -662,10 +500,10 @@ F 3 "" H 1100 7300 50  0001 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L power:GND #PWR033
+L power:GND #PWR032
 U 1 1 6012A85F
 P 1300 7300
-F 0 "#PWR033" H 1300 7050 50  0001 C CNN
+F 0 "#PWR032" H 1300 7050 50  0001 C CNN
 F 1 "GND" H 1305 7127 50  0000 C CNN
 F 2 "" H 1300 7300 50  0001 C CNN
 F 3 "" H 1300 7300 50  0001 C CNN
@@ -677,7 +515,7 @@ L Device:C C18
 U 1 1 6012E342
 P 1300 7100
 F 0 "C18" H 1415 7146 50  0000 L CNN
-F 1 "100n" H 1415 7055 50  0000 L CNN
+F 1 "DNP" H 1415 7055 50  0000 L CNN
 F 2 "Capacitor_SMD:C_0603_1608Metric" H 1338 6950 50  0001 C CNN
 F 3 "~" H 1300 7100 50  0001 C CNN
 	1    1300 7100
@@ -700,10 +538,10 @@ Wire Wire Line
 Wire Wire Line
 	2450 6650 2450 7300
 $Comp
-L power:GND #PWR035
+L power:GND #PWR034
 U 1 1 6013E5C6
 P 2450 7300
-F 0 "#PWR035" H 2450 7050 50  0001 C CNN
+F 0 "#PWR034" H 2450 7050 50  0001 C CNN
 F 1 "GND" H 2455 7127 50  0000 C CNN
 F 2 "" H 2450 7300 50  0001 C CNN
 F 3 "" H 2450 7300 50  0001 C CNN
@@ -728,14 +566,12 @@ Text Label 5500 4950 2    50   ~ 0
 SWCLK
 Text Label 5500 4850 2    50   ~ 0
 SWDIO
-Wire Wire Line
-	5250 5650 5500 5650
 $Sheet
-S 5500 5300 900  1750
+S 7350 4550 900  1750
 U 60184A6B
 F0 "LED Grave" 50
 F1 "led-grave.sch" 50
-F2 "SK6812_DATA_IN" I L 5500 5650 50 
+F2 "SK6812_DATA_IN" I L 7350 4900 50 
 $EndSheet
 $Comp
 L Regulator_Switching:ST1S10PHR U2
@@ -764,10 +600,10 @@ Wire Wire Line
 Wire Wire Line
 	7300 1450 7300 1850
 $Comp
-L power:GND #PWR014
+L power:GND #PWR013
 U 1 1 600A5407
 P 7300 1850
-F 0 "#PWR014" H 7300 1600 50  0001 C CNN
+F 0 "#PWR013" H 7300 1600 50  0001 C CNN
 F 1 "GND" H 7305 1677 50  0000 C CNN
 F 2 "" H 7300 1850 50  0001 C CNN
 F 3 "" H 7300 1850 50  0001 C CNN
@@ -775,10 +611,10 @@ F 3 "" H 7300 1850 50  0001 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L power:GND #PWR015
+L power:GND #PWR014
 U 1 1 600A570A
 P 7800 1850
-F 0 "#PWR015" H 7800 1600 50  0001 C CNN
+F 0 "#PWR014" H 7800 1600 50  0001 C CNN
 F 1 "GND" H 7805 1677 50  0000 C CNN
 F 2 "" H 7800 1850 50  0001 C CNN
 F 3 "" H 7800 1850 50  0001 C CNN
@@ -820,10 +656,10 @@ $EndComp
 Wire Wire Line
 	5950 1600 5950 1700
 $Comp
-L power:GND #PWR013
+L power:GND #PWR012
 U 1 1 600BF873
 P 5950 1850
-F 0 "#PWR013" H 5950 1600 50  0001 C CNN
+F 0 "#PWR012" H 5950 1600 50  0001 C CNN
 F 1 "GND" H 5955 1677 50  0000 C CNN
 F 2 "" H 5950 1850 50  0001 C CNN
 F 3 "" H 5950 1850 50  0001 C CNN
@@ -901,7 +737,7 @@ U 1 1 600E5144
 P 9400 1500
 F 0 "C7" H 9515 1546 50  0000 L CNN
 F 1 "10u" H 9515 1455 50  0000 L CNN
-F 2 "Capacitor_SMD:C_1210_3225Metric" H 9438 1350 50  0001 C CNN
+F 2 "Capacitor_SMD:C_0805_2012Metric" H 9438 1350 50  0001 C CNN
 F 3 "~" H 9400 1500 50  0001 C CNN
 	1    9400 1500
 	1    0    0    -1  
@@ -912,7 +748,7 @@ U 1 1 600E635C
 P 9750 1500
 F 0 "C8" H 9865 1546 50  0000 L CNN
 F 1 "10u" H 9865 1455 50  0000 L CNN
-F 2 "Capacitor_SMD:C_1210_3225Metric" H 9788 1350 50  0001 C CNN
+F 2 "Capacitor_SMD:C_0805_2012Metric" H 9788 1350 50  0001 C CNN
 F 3 "~" H 9750 1500 50  0001 C CNN
 	1    9750 1500
 	1    0    0    -1  
@@ -923,7 +759,7 @@ U 1 1 600E6713
 P 10100 1500
 F 0 "C9" H 10215 1546 50  0000 L CNN
 F 1 "10u" H 10215 1455 50  0000 L CNN
-F 2 "Capacitor_SMD:C_1210_3225Metric" H 10138 1350 50  0001 C CNN
+F 2 "Capacitor_SMD:C_0805_2012Metric" H 10138 1350 50  0001 C CNN
 F 3 "~" H 10100 1500 50  0001 C CNN
 	1    10100 1500
 	1    0    0    -1  
@@ -934,7 +770,7 @@ U 1 1 600E7362
 P 10450 1500
 F 0 "C10" H 10565 1546 50  0000 L CNN
 F 1 "10u" H 10565 1455 50  0000 L CNN
-F 2 "Capacitor_SMD:C_1210_3225Metric" H 10488 1350 50  0001 C CNN
+F 2 "Capacitor_SMD:C_0805_2012Metric" H 10488 1350 50  0001 C CNN
 F 3 "~" H 10450 1500 50  0001 C CNN
 	1    10450 1500
 	1    0    0    -1  
@@ -1068,10 +904,10 @@ F 3 "" H 9000 1000 50  0001 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L Device:R R3
+L Device:R R1
 U 1 1 6014E774
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-F 0 "R3" H 8720 1796 50  0000 L CNN
+F 0 "R1" H 8720 1796 50  0000 L CNN
 F 1 "5k36" H 8720 1705 50  0000 L CNN
 F 2 "Resistor_SMD:R_0603_1608Metric" V 8580 1750 50  0001 C CNN
 F 3 "~" H 8650 1750 50  0001 C CNN
@@ -1079,10 +915,10 @@ F 3 "~" H 8650 1750 50  0001 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L Device:R R6
+L Device:R R3
 U 1 1 6014EC41
 P 8650 2150
-F 0 "R6" H 8720 2196 50  0000 L CNN
+F 0 "R3" H 8720 2196 50  0000 L CNN
 F 1 "1k" H 8720 2105 50  0000 L CNN
 F 2 "Resistor_SMD:R_0603_1608Metric" V 8580 2150 50  0001 C CNN
 F 3 "~" H 8650 2150 50  0001 C CNN
@@ -1110,10 +946,10 @@ Wire Wire Line
 	8250 1800 8000 1800
 Connection ~ 8000 1800
 $Comp
-L power:+5V #PWR018
+L power:+5V #PWR016
 U 1 1 6018E9C1
 P 7350 2700
-F 0 "#PWR018" H 7350 2550 50  0001 C CNN
+F 0 "#PWR016" H 7350 2550 50  0001 C CNN
 F 1 "+5V" H 7365 2873 50  0000 C CNN
 F 2 "" H 7350 2700 50  0001 C CNN
 F 3 "" H 7350 2700 50  0001 C CNN
@@ -1127,10 +963,10 @@ Wire Wire Line
 Wire Wire Line
 	7800 3100 7800 3150
 $Comp
-L power:GND #PWR020
+L power:GND #PWR018
 U 1 1 6019C453
 P 7800 3200
-F 0 "#PWR020" H 7800 2950 50  0001 C CNN
+F 0 "#PWR018" H 7800 2950 50  0001 C CNN
 F 1 "GND" H 7805 3027 50  0000 C CNN
 F 2 "" H 7800 3200 50  0001 C CNN
 F 3 "" H 7800 3200 50  0001 C CNN
@@ -1161,29 +997,23 @@ Wire Wire Line
 	8300 2800 8300 2700
 Connection ~ 8300 2800
 $Comp
-L power:+3V3 #PWR019
+L power:+3V3 #PWR017
 U 1 1 601B9175
 P 8300 2700
-F 0 "#PWR019" H 8300 2550 50  0001 C CNN
+F 0 "#PWR017" H 8300 2550 50  0001 C CNN
 F 1 "+3V3" H 8315 2873 50  0000 C CNN
 F 2 "" H 8300 2700 50  0001 C CNN
 F 3 "" H 8300 2700 50  0001 C CNN
 	1    8300 2700
 	1    0    0    -1  
 $EndComp
-Text Label 5500 4350 2    50   ~ 0
-DMX_~RXEN
 Wire Wire Line
 	5500 4350 5000 4350
-Text Label 5500 4250 2    50   ~ 0
-DMX_TXEN
-Wire Wire Line
-	5500 4250 5000 4250
 $Comp
-L power:+12V #PWR05
+L power:+12V #PWR02
 U 1 1 602651C8
 P 2300 850
-F 0 "#PWR05" H 2300 700 50  0001 C CNN
+F 0 "#PWR02" H 2300 700 50  0001 C CNN
 F 1 "+12V" H 2315 1023 50  0000 C CNN
 F 2 "" H 2300 850 50  0001 C CNN
 F 3 "" H 2300 850 50  0001 C CNN
@@ -1222,13 +1052,13 @@ Wire Wire Line
 	1600 1200 1600 1100
 NoConn ~ 2150 1300
 $Comp
-L Switch:SW_SPDT SW2
+L Switch:SW_SPDT SW1
 U 1 1 601264C2
 P 1950 1200
-F 0 "SW2" H 1950 875 50  0000 C CNN
+F 0 "SW1" H 1950 875 50  0000 C CNN
 F 1 "5FS1S102M6QE " H 1950 966 50  0000 C CNN
 F 2 "shimatta_switch:NINIGI-5FS1S102M6QE" H 1950 1200 50  0001 C CNN
-F 3 "~" H 1950 1200 50  0001 C CNN
+F 3 "https://www.tme.eu/Document/d3fdab2d1ef2b3e44d3477e847fc8839/slide_switch_5F.PDF" H 1950 1200 50  0001 C CNN
 	1    1950 1200
 	1    0    0    1   
 $EndComp
@@ -1251,36 +1081,19 @@ Wire Wire Line
 	1000 1500 1000 1400
 Wire Wire Line
 	1000 1400 950  1400
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-U 1 1 60190060
-P 3700 7350
-F 0 "H1" H 3800 7396 50  0000 L CNN
-F 1 "MountingHole" H 3800 7305 50  0000 L CNN
-F 2 "MountingHole:MountingHole_3.2mm_M3" H 3700 7350 50  0001 C CNN
-F 3 "~" H 3700 7350 50  0001 C CNN
-	1    3700 7350
-	1    0    0    -1  
-$EndComp
 Wire Wire Line
 	1400 1200 950  1200
 Wire Wire Line
 	1400 1200 1400 1950
 Wire Wire Line
 	1500 1300 950  1300
-Wire Wire Line
-	5250 5650 5250 5150
-Wire Wire Line
-	5250 5150 6450 5150
-Wire Wire Line
-	6450 5150 6450 4150
 Wire Wire Line
 	5000 4150 6450 4150
 $Comp
-L Device:R R11
+L Device:R R8
 U 1 1 601FEE20
 P 5800 4950
-F 0 "R11" H 5870 4996 50  0000 L CNN
+F 0 "R8" H 5870 4996 50  0000 L CNN
 F 1 "10k" H 5870 4905 50  0000 L CNN
 F 2 "Resistor_SMD:R_0603_1608Metric" V 5730 4950 50  0001 C CNN
 F 3 "~" H 5800 4950 50  0001 C CNN
@@ -1294,10 +1107,10 @@ Wire Wire Line
 Wire Wire Line
 	6050 4950 6050 5000
 $Comp
-L power:GND #PWR0129
+L power:GND #PWR024
 U 1 1 6021011C
 P 6050 5000
-F 0 "#PWR0129" H 6050 4750 50  0001 C CNN
+F 0 "#PWR024" H 6050 4750 50  0001 C CNN
 F 1 "GND" H 6055 4827 50  0000 C CNN
 F 2 "" H 6050 5000 50  0001 C CNN
 F 3 "" H 6050 5000 50  0001 C CNN
@@ -1305,10 +1118,10 @@ F 3 "" H 6050 5000 50  0001 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L Device:R R10
+L Device:R R7
 U 1 1 60210BDA
 P 5800 4850
-F 0 "R10" H 5870 4896 50  0000 L CNN
+F 0 "R7" H 5870 4896 50  0000 L CNN
 F 1 "10k" H 5870 4805 50  0000 L CNN
 F 2 "Resistor_SMD:R_0603_1608Metric" V 5730 4850 50  0001 C CNN
 F 3 "~" H 5800 4850 50  0001 C CNN
@@ -1322,36 +1135,242 @@ Wire Wire Line
 Wire Wire Line
 	6050 4850 6050 4750
 $Comp
-L power:+3V3 #PWR0130
+L power:+3V3 #PWR023
 U 1 1 60222D01
 P 6050 4750
-F 0 "#PWR0130" H 6050 4600 50  0001 C CNN
+F 0 "#PWR023" H 6050 4600 50  0001 C CNN
 F 1 "+3V3" H 6065 4923 50  0000 C CNN
 F 2 "" H 6050 4750 50  0001 C CNN
 F 3 "" H 6050 4750 50  0001 C CNN
 	1    6050 4750
 	1    0    0    -1  
 $EndComp
+Wire Wire Line
+	3400 4050 4000 4050
+Wire Wire Line
+	3100 4050 3000 4050
+Wire Wire Line
+	3000 4050 3000 4200
 $Comp
-L Mechanical:MountingHole H2
-U 1 1 6021B3E3
-P 3700 7600
-F 0 "H2" H 3800 7646 50  0000 L CNN
-F 1 "MountingHole" H 3800 7555 50  0000 L CNN
-F 2 "MountingHole:MountingHole_3.2mm_M3" H 3700 7600 50  0001 C CNN
-F 3 "~" H 3700 7600 50  0001 C CNN
-	1    3700 7600
+L power:GND #PWR022
+U 1 1 605FA399
+P 3000 4200
+F 0 "#PWR022" H 3000 3950 50  0001 C CNN
+F 1 "GND" H 3005 4027 50  0000 C CNN
+F 2 "" H 3000 4200 50  0001 C CNN
+F 3 "" H 3000 4200 50  0001 C CNN
+	1    3000 4200
+	1    0    0    -1  
+$EndComp
+NoConn ~ 1500 4100
+NoConn ~ 1500 4800
+NoConn ~ 1500 4900
+Text Label 4950 1700 2    50   ~ 0
+DMX_~RX~TX
+Wire Wire Line
+	4050 1700 4950 1700
+Wire Wire Line
+	4050 1500 4950 1500
+Wire Wire Line
+	4050 1400 4950 1400
+Text Label 5500 4350 2    50   ~ 0
+DMX_~RX~TX
+Wire Wire Line
+	4000 4950 3600 4950
+Wire Wire Line
+	3600 4950 3600 5400
+Text Label 3600 5400 1    50   ~ 0
+WHITE_PWM
+NoConn ~ 5000 4050
+NoConn ~ 5000 3950
+$Sheet
+S 9450 4550 700  1800
+U 606770DB
+F0 "WhiteLEDs" 50
+F1 "WhiteLEDs.sch" 50
+F2 "PWM" I L 9450 4950 50 
+$EndSheet
+Wire Wire Line
+	7350 4900 6450 4900
+Wire Wire Line
+	6450 4900 6450 4150
+Wire Wire Line
+	9450 4950 8850 4950
+Text Label 8850 4950 0    50   ~ 0
+WHITE_PWM
+NoConn ~ 5000 4250
+Wire Wire Line
+	3550 4750 4000 4750
+$Comp
+L Connector:TestPoint TP1
+U 1 1 60615CD7
+P 3700 6750
+F 0 "TP1" H 3758 6868 50  0000 L CNN
+F 1 "GND" H 3758 6777 50  0000 L CNN
+F 2 "TestPoint:TestPoint_Loop_D2.60mm_Drill0.9mm_Beaded" H 3900 6750 50  0001 C CNN
+F 3 "~" H 3900 6750 50  0001 C CNN
+	1    3700 6750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3700 6750 3700 6850
+$Comp
+L power:GND #PWR0146
+U 1 1 6062089C
+P 3700 6850
+F 0 "#PWR0146" H 3700 6600 50  0001 C CNN
+F 1 "GND" H 3705 6677 50  0000 C CNN
+F 2 "" H 3700 6850 50  0001 C CNN
+F 3 "" H 3700 6850 50  0001 C CNN
+	1    3700 6850
 	1    0    0    -1  
 $EndComp
 $Comp
-L Mechanical:MountingHole H3
-U 1 1 6022C057
-P 4600 7350
-F 0 "H3" H 4700 7396 50  0000 L CNN
-F 1 "MountingHole" H 4700 7305 50  0000 L CNN
-F 2 "MountingHole:MountingHole_2.2mm_M2" H 4600 7350 50  0001 C CNN
-F 3 "~" H 4600 7350 50  0001 C CNN
-	1    4600 7350
+L Connector:TestPoint TP2
+U 1 1 60620B38
+P 4100 6750
+F 0 "TP2" H 4158 6868 50  0000 L CNN
+F 1 "5V" H 4158 6777 50  0000 L CNN
+F 2 "TestPoint:TestPoint_Pad_D1.5mm" H 4300 6750 50  0001 C CNN
+F 3 "~" H 4300 6750 50  0001 C CNN
+	1    4100 6750
+	1    0    0    -1  
+$EndComp
+$Comp
+L Connector:TestPoint TP3
+U 1 1 60620DCD
+P 4450 6750
+F 0 "TP3" H 4508 6868 50  0000 L CNN
+F 1 "12V" H 4508 6777 50  0000 L CNN
+F 2 "TestPoint:TestPoint_Pad_D1.5mm" H 4650 6750 50  0001 C CNN
+F 3 "~" H 4650 6750 50  0001 C CNN
+	1    4450 6750
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	4100 6750 4100 6850
+$Comp
+L power:+5V #PWR0147
+U 1 1 606288DC
+P 4100 6850
+F 0 "#PWR0147" H 4100 6700 50  0001 C CNN
+F 1 "+5V" H 4115 7023 50  0000 C CNN
+F 2 "" H 4100 6850 50  0001 C CNN
+F 3 "" H 4100 6850 50  0001 C CNN
+	1    4100 6850
+	-1   0    0    1   
+$EndComp
+$Comp
+L power:+12V #PWR0148
+U 1 1 6063208C
+P 4450 6850
+F 0 "#PWR0148" H 4450 6700 50  0001 C CNN
+F 1 "+12V" H 4465 7023 50  0000 C CNN
+F 2 "" H 4450 6850 50  0001 C CNN
+F 3 "" H 4450 6850 50  0001 C CNN
+	1    4450 6850
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4450 6850 4450 6750
+$Comp
+L Mechanical:MountingHole_Pad H1
+U 1 1 606C8089
+P 3400 7400
+F 0 "H1" H 3500 7449 50  0000 L CNN
+F 1 "MountingHole_Pad" H 3500 7358 50  0000 L CNN
+F 2 "MountingHole:MountingHole_3.2mm_M3_Pad_Via" H 3400 7400 50  0001 C CNN
+F 3 "~" H 3400 7400 50  0001 C CNN
+	1    3400 7400
+	1    0    0    -1  
+$EndComp
+$Comp
+L Mechanical:MountingHole_Pad H2
+U 1 1 606C8903
+P 3750 7400
+F 0 "H2" H 3850 7449 50  0000 L CNN
+F 1 "MountingHole_Pad" H 3850 7358 50  0000 L CNN
+F 2 "MountingHole:MountingHole_3.2mm_M3_Pad_Via" H 3750 7400 50  0001 C CNN
+F 3 "~" H 3750 7400 50  0001 C CNN
+	1    3750 7400
+	1    0    0    -1  
+$EndComp
+$Comp
+L Mechanical:MountingHole_Pad H3
+U 1 1 606C8BF2
+P 4050 7400
+F 0 "H3" H 4150 7449 50  0000 L CNN
+F 1 "MountingHole_Pad" H 4150 7358 50  0000 L CNN
+F 2 "MountingHole:MountingHole_3.2mm_M3_Pad_Via" H 4050 7400 50  0001 C CNN
+F 3 "~" H 4050 7400 50  0001 C CNN
+	1    4050 7400
+	1    0    0    -1  
+$EndComp
+$Comp
+L Mechanical:MountingHole_Pad H4
+U 1 1 606C916E
+P 4350 7400
+F 0 "H4" H 4450 7449 50  0000 L CNN
+F 1 "MountingHole_Pad" H 4450 7358 50  0000 L CNN
+F 2 "MountingHole:MountingHole_3.2mm_M3_Pad_Via" H 4350 7400 50  0001 C CNN
+F 3 "~" H 4350 7400 50  0001 C CNN
+	1    4350 7400
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3400 7500 3400 7550
+Wire Wire Line
+	3400 7550 3750 7550
+Wire Wire Line
+	4350 7550 4350 7500
+Wire Wire Line
+	4050 7500 4050 7550
+Connection ~ 4050 7550
+Wire Wire Line
+	4050 7550 4350 7550
+Wire Wire Line
+	3750 7500 3750 7550
+Connection ~ 3750 7550
+Wire Wire Line
+	3750 7550 3900 7550
+Wire Wire Line
+	3900 7550 3900 7600
+Connection ~ 3900 7550
+Wire Wire Line
+	3900 7550 4050 7550
+$Comp
+L power:GND #PWR0149
+U 1 1 606E84B1
+P 3900 7600
+F 0 "#PWR0149" H 3900 7350 50  0001 C CNN
+F 1 "GND" H 3905 7427 50  0000 C CNN
+F 2 "" H 3900 7600 50  0001 C CNN
+F 3 "" H 3900 7600 50  0001 C CNN
+	1    3900 7600
+	1    0    0    -1  
+$EndComp
+$Comp
+L shimatta_connectors:Rotary_Encoder_Switch_Mounting SW2
+U 1 1 606929D5
+P 2050 6550
+F 0 "SW2" H 2050 6917 50  0000 C CNN
+F 1 "EN11-VSM" H 2050 6826 50  0000 C CNN
+F 2 "shimatta_switch:EN11-VSM" H 1900 6710 50  0001 C CNN
+F 3 "~" H 2050 6810 50  0001 C CNN
+	1    2050 6550
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	2050 6850 2050 7300
+$Comp
+L power:GND #PWR0150
+U 1 1 606A1879
+P 2050 7300
+F 0 "#PWR0150" H 2050 7050 50  0001 C CNN
+F 1 "GND" H 2055 7127 50  0000 C CNN
+F 2 "" H 2050 7300 50  0001 C CNN
+F 3 "" H 2050 7300 50  0001 C CNN
+	1    2050 7300
 	1    0    0    -1  
 $EndComp
 $EndSCHEMATC