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dvi-fpga
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Mario Hüttel
716c1b88e5
fixed cap in VIO for FPGA, added project/my name and date
2017-01-04 03:07:54 +01:00
dvi.pretty
finished component association
2016-12-11 17:37:27 +01:00
.gitignore
added gerber files to gitignore
2017-01-01 20:45:27 +01:00
con-molex.lib
added tfp 401 and dvi connector
2016-11-27 15:53:52 +01:00
dvi_in.sch
layout, added cap in 3v3
2016-12-13 15:31:47 +01:00
dvi_out.sch
layout, added cap in 3v3
2016-12-13 15:31:47 +01:00
dvi-sniffer-cache.lib
flipped resistor arrays, started layout
2016-12-11 18:30:16 +01:00
dvi-sniffer.kicad_pcb
fixed cap in VIO for FPGA, added project/my name and date
2017-01-04 03:07:54 +01:00
dvi-sniffer.net
finished first draft
2016-12-13 20:25:47 +01:00
dvi-sniffer.pro
added tfp 401 and dvi connector
2016-11-27 15:53:52 +01:00
dvi-sniffer.sch
unified rsistor array sizes, associated components
2016-12-10 16:58:19 +01:00
fp-lib-table
added symbols, fixed silkscreen, last changes
2017-01-01 20:34:59 +01:00
fpga.sch
finished first draft
2016-12-13 20:25:47 +01:00
power.sch
finished component association
2016-12-11 17:37:27 +01:00
powersym.dcm
added v_io symbol, video_in bus
2016-11-27 13:43:11 +01:00
powersym.lib
added v_io symbol, video_in bus
2016-11-27 13:43:11 +01:00
Description
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4
MiB
Languages
KiCad Layout
89.9%
KiCad Schematic
10.1%
