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Fix missing in assignment in port

This commit is contained in:
Mario Hüttel 2020-08-10 22:41:29 +02:00
parent 6d7492a98d
commit b64af9e9de
1 changed files with 2 additions and 2 deletions
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4
design/smi.vhd
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@ -44,8 +44,8 @@ entity smi is
busy_o : out std_logic;
data_o : out std_logic_vector(15 downto 0);
data_o_strb : out std_logic;
phyaddr_i : std_logic_vector(4 downto 0);
regaddr_i : std_logic_vector(4 downto 0);
phyaddr_i : in std_logic_vector(4 downto 0);
regaddr_i : in std_logic_vector(4 downto 0);
data_i : in std_logic_vector(15 downto 0);
strb_i : in std_logic;
rw_i : in std_logic --Read/write. 0=write, 1=read