fpga/axi3-interconnect
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1ce3f9c97bd6173abf0dc7f6170df88248e0db5d
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Mario Hüttel 1ce3f9c97b Add simulation for toplevel
2020-03-10 20:06:17 +01:00
.settings
started type definitions
2016-08-20 14:43:06 +02:00
sim
Add simulation for toplevel
2020-03-10 20:06:17 +01:00
src
Add simulation for toplevel
2020-03-10 20:06:17 +01:00
.gitignore
started type definitions
2016-08-20 14:43:06 +02:00
.library_mapping.xml
remove package body, changed aliases to subtypes
2016-08-20 18:08:38 +02:00
.project
started type definitions
2016-08-20 14:43:06 +02:00
LICENSE.txt
Added GPLv2 License
2016-12-05 15:00:02 +01:00
Description
AXI3 crossbar interconnect
64 KiB
Languages
VHDL 99.3%
Shell 0.7%