Add simulation for toplevel

sim/.gitignore

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+*.o
+*.ghw

sim/import-sources.sh

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+#!/bin/bash
+
+if [[ -z $1 ]]; then
+	echo "Specify object directory"
+	exit -1
+fi
+
+if [[ -z $2 ]]; then
+	echo "Specify source folder to scan"
+	exit -1
+fi
+
+
+if [[ -z $3 ]]; then
+	echo "Specify target library"
+	exit -1
+fi
+
+echo "Scanning \"$2\" for lib \"$3\" to obj dir \"$1\""
+
+files=`find "$2" -name "*.vhd"`
+
+for file in $files; do
+	echo "Importing file $file"
+	ghdl -i --workdir="$1" --work="$3" "$file"
+done

sim/toplevel_sim/.gitignore

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+bench

sim/toplevel_sim/top_bench.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library design;
+use design.all;
+use design.axi3intercon_pkg.all;
+
+
+entity bench is
+
+end entity bench;
+
+architecture sim of bench is
+
+	constant addresses : axi_slave_addresses_t := (0 => (others => '1'));
+	constant masks	   : axi_slave_addresses_t := (0 => (0 => '0', 1 => '0', others => '1'));
+
+	signal slaves_out  : axi_slaves_out_t(0 to 0);
+	signal masters_out : axi_masters_out_t(0 to 0);
+	signal masters_in  : axi_masters_in_t(0 to 0);
+
+	signal aclk    : std_logic;
+	signal aresetn : std_logic;
+
+
+begin  -- architecture sim
+
+
+	clkgen : process is
+	begin
+		aclk <= '0';
+		wait for 20 ns;
+		aclk <= '1';
+		wait for 20 ns;
+	end process clkgen;
+
+	rstgen : process is
+	begin
+		aresetn <= '0';
+		wait for 30 ns;
+		aresetn <= '1';
+		wait;
+	end process rstgen;
+
+	test : process is
+	begin
+		wait until rising_edge(aclk);
+		wait until rising_edge(aclk);
+		wait for 100 ns;
+
+		masters_out(0).w.wvalid <= '0';
+		masters_out(0).w.wlast	<= '0';
+
+		wait until rising_edge(aclk);
+
+		masters_out(0).ar.arid	 <= (3 => '0', others => '1');
+		masters_out(0).ar.araddr <= (2 => '1', 4 => '1', others => '0');
+
+		masters_out(0).ar.arlen	  <= std_logic_vector(to_unsigned(9, 8));
+		masters_out(0).ar.arburst <= (others => '0');
+		masters_out(0).ar.arprot  <= (others => '0');
+		masters_out(0).ar.arsize  <= (1	     => '1', others => '0');
+		masters_out(0).ar.arvalid <= '1';
+		wait until rising_edge(aclk) and masters_in(0).ar.arready = '1';
+		masters_out(0).ar.arvalid <= '0';
+
+
+		wait until rising_edge(aclk);
+		-- Issue write request
+		masters_out(0).aw.awid	  <= (5	     => '1', others => '0');
+		masters_out(0).aw.awaddr  <= (4	     => '1', others => '0');
+		masters_out(0).aw.awlen	  <= std_logic_vector(to_unsigned(1, 8));
+		masters_out(0).aw.awsize  <= (others => '0');
+		masters_out(0).aw.awburst <= (others => '0');
+		masters_out(0).aw.awlock  <= (others => '0');
+		masters_out(0).aw.awcache <= (others => '0');
+		masters_out(0).aw.awprot  <= (others => '0');
+		masters_out(0).aw.awvalid <= '1';
+		wait until rising_edge(aclk) and masters_in(0).aw.awready = '1';
+		masters_out(0).aw.awvalid <= '0';
+
+		masters_out(0).w.wstrb	<= (others => '1');
+		masters_out(0).w.wdata	<= x"DEADBEEF";
+		masters_out(0).w.wlast	<= '0';
+		masters_out(0).w.wid	<= (5	   => '1', others => '0');
+		masters_out(0).w.wvalid <= '1';
+		wait until rising_edge(aclk) and masters_in(0).w.wready = '1';
+		masters_out(0).w.wvalid <= '1';
+		masters_out(0).w.wdata	<= x"CAFEBABE";
+		masters_out(0).w.wlast	<= '1';
+		wait until rising_edge(aclk) and masters_in(0).w.wready = '1';
+		masters_out(0).w.wvalid <= '0';
+
+
+		wait;
+	end process;
+
+	b_acceptor : process is
+	begin
+		masters_out(0).b.bready <= '0';
+		wait until rising_edge(aclk) and masters_in(0).b.bvalid = '1';
+		report "b_acceptor: Received B channel response wit BID " &
+			integer'image(to_integer(unsigned(masters_in(0).b.bid)));
+		masters_out(0).b.bready <= '1';
+		wait until rising_edge(aclk);
+
+	end process b_acceptor;
+
+	read_acceptor : process is
+	begin
+		masters_out(0).r.rready <= '0';
+		wait until rising_edge(aclk) and masters_in(0).r.rvalid = '1';
+		report "read_acceptor: Received read with RID " &
+			integer'image(to_integer(unsigned(masters_in(0).r.rid)));
+		report "read_acceptor: RLAST is " & std_logic'image(masters_in(0).r.rlast);
+		masters_out(0).r.rready <= '1';
+		wait until rising_edge(aclk);
+
+	end process read_acceptor;
+
+	axi3intercon_1 : entity design.axi3intercon
+		port map (
+			aclk	      => aclk,
+			aresetn	      => aresetn,
+			masters_in    => masters_in,
+			masters_out   => masters_out,
+			slaves_in     => open,
+			slaves_out    => slaves_out,
+			address_array => addresses,
+			mask_array    => masks);
+
+end architecture sim;

sim/toplevel_sim/toplevel-sim.gtkw

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+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Tue Mar 10 18:44:35 2020
+[*]
+[dumpfile] "/home/mari/projects/fpga/axi3-interconnect/sim/toplevel_sim/wave.ghw"
+[dumpfile_mtime] "Tue Mar 10 18:29:29 2020"
+[dumpfile_size] 56058
+[savefile] "/home/mari/projects/fpga/axi3-interconnect/sim/toplevel_sim/toplevel-sim.gtkw"
+[timestart] 0
+[size] 1920 1016
+[pos] -39 -39
+*-28.000000 180000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] top.
+[treeopen] top.bench.
+[treeopen] top.bench.masters_in.
+[treeopen] top.bench.masters_in.[0].
+[treeopen] top.bench.masters_in.[0].b.
+[treeopen] top.bench.masters_out.
+[treeopen] top.bench.masters_out.[0].
+[treeopen] top.bench.masters_out.[0].ar.
+[treeopen] top.bench.slaves_out.[0].
+[treeopen] top.bench.slaves_out.[0].b.
+[sst_width] 464
+[signals_width] 307
+[sst_expanded] 1
+[sst_vpaned_height] 286
+@28
+top.bench.aresetn
+top.bench.aclk
+@200
+-Master
+-Write Channel
+@22
+#{top.bench.masters_out[0].w.wuser[3:0]} top.bench.masters_out[0].w.wuser[3] top.bench.masters_out[0].w.wuser[2] top.bench.masters_out[0].w.wuser[1] top.bench.masters_out[0].w.wuser[0]
+#{top.bench.masters_out[0].w.wstrb[3:0]} top.bench.masters_out[0].w.wstrb[3] top.bench.masters_out[0].w.wstrb[2] top.bench.masters_out[0].w.wstrb[1] top.bench.masters_out[0].w.wstrb[0]
+#{top.bench.masters_out[0].w.wdata[31:0]} top.bench.masters_out[0].w.wdata[31] top.bench.masters_out[0].w.wdata[30] top.bench.masters_out[0].w.wdata[29] top.bench.masters_out[0].w.wdata[28] top.bench.masters_out[0].w.wdata[27] top.bench.masters_out[0].w.wdata[26] top.bench.masters_out[0].w.wdata[25] top.bench.masters_out[0].w.wdata[24] top.bench.masters_out[0].w.wdata[23] top.bench.masters_out[0].w.wdata[22] top.bench.masters_out[0].w.wdata[21] top.bench.masters_out[0].w.wdata[20] top.bench.masters_out[0].w.wdata[19] top.bench.masters_out[0].w.wdata[18] top.bench.masters_out[0].w.wdata[17] top.bench.masters_out[0].w.wdata[16] top.bench.masters_out[0].w.wdata[15] top.bench.masters_out[0].w.wdata[14] top.bench.masters_out[0].w.wdata[13] top.bench.masters_out[0].w.wdata[12] top.bench.masters_out[0].w.wdata[11] top.bench.masters_out[0].w.wdata[10] top.bench.masters_out[0].w.wdata[9] top.bench.masters_out[0].w.wdata[8] top.bench.masters_out[0].w.wdata[7] top.bench.masters_out[0].w.wdata[6] top.bench.masters_out[0].w.wdata[5] top.bench.masters_out[0].w.wdata[4] top.bench.masters_out[0].w.wdata[3] top.bench.masters_out[0].w.wdata[2] top.bench.masters_out[0].w.wdata[1] top.bench.masters_out[0].w.wdata[0]
+#{top.bench.masters_out[0].w.wid[11:0]} top.bench.masters_out[0].w.wid[11] top.bench.masters_out[0].w.wid[10] top.bench.masters_out[0].w.wid[9] top.bench.masters_out[0].w.wid[8] top.bench.masters_out[0].w.wid[7] top.bench.masters_out[0].w.wid[6] top.bench.masters_out[0].w.wid[5] top.bench.masters_out[0].w.wid[4] top.bench.masters_out[0].w.wid[3] top.bench.masters_out[0].w.wid[2] top.bench.masters_out[0].w.wid[1] top.bench.masters_out[0].w.wid[0]
+@28
+top.bench.masters_out[0].w.wlast
+top.bench.masters_out[0].w.wvalid
+top.bench.masters_in[0].w.wready
+@200
+-
+-Write Address Channel
+@28
+#{top.bench.masters_out[0].aw.awprot[2:0]} top.bench.masters_out[0].aw.awprot[2] top.bench.masters_out[0].aw.awprot[1] top.bench.masters_out[0].aw.awprot[0]
+@22
+#{top.bench.masters_out[0].aw.awcache[3:0]} top.bench.masters_out[0].aw.awcache[3] top.bench.masters_out[0].aw.awcache[2] top.bench.masters_out[0].aw.awcache[1] top.bench.masters_out[0].aw.awcache[0]
+@28
+#{top.bench.masters_out[0].aw.awlock[1:0]} top.bench.masters_out[0].aw.awlock[1] top.bench.masters_out[0].aw.awlock[0]
+#{top.bench.masters_out[0].aw.awsize[2:0]} top.bench.masters_out[0].aw.awsize[2] top.bench.masters_out[0].aw.awsize[1] top.bench.masters_out[0].aw.awsize[0]
+#{top.bench.masters_out[0].aw.awburst[1:0]} top.bench.masters_out[0].aw.awburst[1] top.bench.masters_out[0].aw.awburst[0]
+@22
+#{top.bench.masters_out[0].aw.awlen[7:0]} top.bench.masters_out[0].aw.awlen[7] top.bench.masters_out[0].aw.awlen[6] top.bench.masters_out[0].aw.awlen[5] top.bench.masters_out[0].aw.awlen[4] top.bench.masters_out[0].aw.awlen[3] top.bench.masters_out[0].aw.awlen[2] top.bench.masters_out[0].aw.awlen[1] top.bench.masters_out[0].aw.awlen[0]
+#{top.bench.masters_out[0].aw.awaddr[31:0]} top.bench.masters_out[0].aw.awaddr[31] top.bench.masters_out[0].aw.awaddr[30] top.bench.masters_out[0].aw.awaddr[29] top.bench.masters_out[0].aw.awaddr[28] top.bench.masters_out[0].aw.awaddr[27] top.bench.masters_out[0].aw.awaddr[26] top.bench.masters_out[0].aw.awaddr[25] top.bench.masters_out[0].aw.awaddr[24] top.bench.masters_out[0].aw.awaddr[23] top.bench.masters_out[0].aw.awaddr[22] top.bench.masters_out[0].aw.awaddr[21] top.bench.masters_out[0].aw.awaddr[20] top.bench.masters_out[0].aw.awaddr[19] top.bench.masters_out[0].aw.awaddr[18] top.bench.masters_out[0].aw.awaddr[17] top.bench.masters_out[0].aw.awaddr[16] top.bench.masters_out[0].aw.awaddr[15] top.bench.masters_out[0].aw.awaddr[14] top.bench.masters_out[0].aw.awaddr[13] top.bench.masters_out[0].aw.awaddr[12] top.bench.masters_out[0].aw.awaddr[11] top.bench.masters_out[0].aw.awaddr[10] top.bench.masters_out[0].aw.awaddr[9] top.bench.masters_out[0].aw.awaddr[8] top.bench.masters_out[0].aw.awaddr[7] top.bench.masters_out[0].aw.awaddr[6] top.bench.masters_out[0].aw.awaddr[5] top.bench.masters_out[0].aw.awaddr[4] top.bench.masters_out[0].aw.awaddr[3] top.bench.masters_out[0].aw.awaddr[2] top.bench.masters_out[0].aw.awaddr[1] top.bench.masters_out[0].aw.awaddr[0]
+#{top.bench.masters_out[0].aw.awid[11:0]} top.bench.masters_out[0].aw.awid[11] top.bench.masters_out[0].aw.awid[10] top.bench.masters_out[0].aw.awid[9] top.bench.masters_out[0].aw.awid[8] top.bench.masters_out[0].aw.awid[7] top.bench.masters_out[0].aw.awid[6] top.bench.masters_out[0].aw.awid[5] top.bench.masters_out[0].aw.awid[4] top.bench.masters_out[0].aw.awid[3] top.bench.masters_out[0].aw.awid[2] top.bench.masters_out[0].aw.awid[1] top.bench.masters_out[0].aw.awid[0]
+@28
+top.bench.masters_out[0].aw.awvalid
+top.bench.masters_in[0].aw.awready
+@200
+-
+-Master Read Channel
+@22
+#{top.bench.masters_in[0].r.ruser[3:0]} top.bench.masters_in[0].r.ruser[3] top.bench.masters_in[0].r.ruser[2] top.bench.masters_in[0].r.ruser[1] top.bench.masters_in[0].r.ruser[0]
+@28
+#{top.bench.masters_in[0].r.rresp[1:0]} top.bench.masters_in[0].r.rresp[1] top.bench.masters_in[0].r.rresp[0]
+@22
+#{top.bench.masters_in[0].r.rdata[31:0]} top.bench.masters_in[0].r.rdata[31] top.bench.masters_in[0].r.rdata[30] top.bench.masters_in[0].r.rdata[29] top.bench.masters_in[0].r.rdata[28] top.bench.masters_in[0].r.rdata[27] top.bench.masters_in[0].r.rdata[26] top.bench.masters_in[0].r.rdata[25] top.bench.masters_in[0].r.rdata[24] top.bench.masters_in[0].r.rdata[23] top.bench.masters_in[0].r.rdata[22] top.bench.masters_in[0].r.rdata[21] top.bench.masters_in[0].r.rdata[20] top.bench.masters_in[0].r.rdata[19] top.bench.masters_in[0].r.rdata[18] top.bench.masters_in[0].r.rdata[17] top.bench.masters_in[0].r.rdata[16] top.bench.masters_in[0].r.rdata[15] top.bench.masters_in[0].r.rdata[14] top.bench.masters_in[0].r.rdata[13] top.bench.masters_in[0].r.rdata[12] top.bench.masters_in[0].r.rdata[11] top.bench.masters_in[0].r.rdata[10] top.bench.masters_in[0].r.rdata[9] top.bench.masters_in[0].r.rdata[8] top.bench.masters_in[0].r.rdata[7] top.bench.masters_in[0].r.rdata[6] top.bench.masters_in[0].r.rdata[5] top.bench.masters_in[0].r.rdata[4] top.bench.masters_in[0].r.rdata[3] top.bench.masters_in[0].r.rdata[2] top.bench.masters_in[0].r.rdata[1] top.bench.masters_in[0].r.rdata[0]
+#{top.bench.masters_in[0].r.rid[11:0]} top.bench.masters_in[0].r.rid[11] top.bench.masters_in[0].r.rid[10] top.bench.masters_in[0].r.rid[9] top.bench.masters_in[0].r.rid[8] top.bench.masters_in[0].r.rid[7] top.bench.masters_in[0].r.rid[6] top.bench.masters_in[0].r.rid[5] top.bench.masters_in[0].r.rid[4] top.bench.masters_in[0].r.rid[3] top.bench.masters_in[0].r.rid[2] top.bench.masters_in[0].r.rid[1] top.bench.masters_in[0].r.rid[0]
+@28
+top.bench.masters_in[0].r.rvalid
+top.bench.masters_in[0].r.rlast
+top.bench.masters_out[0].r.rready
+@200
+-
+-master B Channel
+@28
+#{top.bench.masters_in[0].b.bresp[1:0]} top.bench.masters_in[0].b.bresp[1] top.bench.masters_in[0].b.bresp[0]
+@22
+#{top.bench.masters_in[0].b.bid[11:0]} top.bench.masters_in[0].b.bid[11] top.bench.masters_in[0].b.bid[10] top.bench.masters_in[0].b.bid[9] top.bench.masters_in[0].b.bid[8] top.bench.masters_in[0].b.bid[7] top.bench.masters_in[0].b.bid[6] top.bench.masters_in[0].b.bid[5] top.bench.masters_in[0].b.bid[4] top.bench.masters_in[0].b.bid[3] top.bench.masters_in[0].b.bid[2] top.bench.masters_in[0].b.bid[1] top.bench.masters_in[0].b.bid[0]
+#{top.bench.masters_in[0].b.buser[3:0]} top.bench.masters_in[0].b.buser[3] top.bench.masters_in[0].b.buser[2] top.bench.masters_in[0].b.buser[1] top.bench.masters_in[0].b.buser[0]
+@28
+top.bench.masters_in[0].b.bvalid
+top.bench.masters_out[0].b.bready
+@200
+-
+-Master Read Address Channel
+@28
+#{top.bench.masters_out[0].ar.arprot[2:0]} top.bench.masters_out[0].ar.arprot[2] top.bench.masters_out[0].ar.arprot[1] top.bench.masters_out[0].ar.arprot[0]
+@22
+#{top.bench.masters_out[0].ar.arcache[3:0]} top.bench.masters_out[0].ar.arcache[3] top.bench.masters_out[0].ar.arcache[2] top.bench.masters_out[0].ar.arcache[1] top.bench.masters_out[0].ar.arcache[0]
+@28
+#{top.bench.masters_out[0].ar.arlock[1:0]} top.bench.masters_out[0].ar.arlock[1] top.bench.masters_out[0].ar.arlock[0]
+#{top.bench.masters_out[0].ar.arburst[1:0]} top.bench.masters_out[0].ar.arburst[1] top.bench.masters_out[0].ar.arburst[0]
+@c00023
+#{top.bench.masters_out[0].ar.arsize[2:0]} top.bench.masters_out[0].ar.arsize[2] top.bench.masters_out[0].ar.arsize[1] top.bench.masters_out[0].ar.arsize[0]
+@28
+top.bench.masters_out[0].ar.arsize[2]
+top.bench.masters_out[0].ar.arsize[1]
+top.bench.masters_out[0].ar.arsize[0]
+@1401203
+-group_end
+@c00022
+#{top.bench.masters_out[0].ar.arlen[7:0]} top.bench.masters_out[0].ar.arlen[7] top.bench.masters_out[0].ar.arlen[6] top.bench.masters_out[0].ar.arlen[5] top.bench.masters_out[0].ar.arlen[4] top.bench.masters_out[0].ar.arlen[3] top.bench.masters_out[0].ar.arlen[2] top.bench.masters_out[0].ar.arlen[1] top.bench.masters_out[0].ar.arlen[0]
+@28
+top.bench.masters_out[0].ar.arlen[7]
+top.bench.masters_out[0].ar.arlen[6]
+top.bench.masters_out[0].ar.arlen[5]
+top.bench.masters_out[0].ar.arlen[4]
+top.bench.masters_out[0].ar.arlen[3]
+top.bench.masters_out[0].ar.arlen[2]
+top.bench.masters_out[0].ar.arlen[1]
+top.bench.masters_out[0].ar.arlen[0]
+@1401202
+-group_end
+@22
+#{top.bench.masters_out[0].ar.araddr[31:0]} top.bench.masters_out[0].ar.araddr[31] top.bench.masters_out[0].ar.araddr[30] top.bench.masters_out[0].ar.araddr[29] top.bench.masters_out[0].ar.araddr[28] top.bench.masters_out[0].ar.araddr[27] top.bench.masters_out[0].ar.araddr[26] top.bench.masters_out[0].ar.araddr[25] top.bench.masters_out[0].ar.araddr[24] top.bench.masters_out[0].ar.araddr[23] top.bench.masters_out[0].ar.araddr[22] top.bench.masters_out[0].ar.araddr[21] top.bench.masters_out[0].ar.araddr[20] top.bench.masters_out[0].ar.araddr[19] top.bench.masters_out[0].ar.araddr[18] top.bench.masters_out[0].ar.araddr[17] top.bench.masters_out[0].ar.araddr[16] top.bench.masters_out[0].ar.araddr[15] top.bench.masters_out[0].ar.araddr[14] top.bench.masters_out[0].ar.araddr[13] top.bench.masters_out[0].ar.araddr[12] top.bench.masters_out[0].ar.araddr[11] top.bench.masters_out[0].ar.araddr[10] top.bench.masters_out[0].ar.araddr[9] top.bench.masters_out[0].ar.araddr[8] top.bench.masters_out[0].ar.araddr[7] top.bench.masters_out[0].ar.araddr[6] top.bench.masters_out[0].ar.araddr[5] top.bench.masters_out[0].ar.araddr[4] top.bench.masters_out[0].ar.araddr[3] top.bench.masters_out[0].ar.araddr[2] top.bench.masters_out[0].ar.araddr[1] top.bench.masters_out[0].ar.araddr[0]
+#{top.bench.masters_out[0].ar.arid[11:0]} top.bench.masters_out[0].ar.arid[11] top.bench.masters_out[0].ar.arid[10] top.bench.masters_out[0].ar.arid[9] top.bench.masters_out[0].ar.arid[8] top.bench.masters_out[0].ar.arid[7] top.bench.masters_out[0].ar.arid[6] top.bench.masters_out[0].ar.arid[5] top.bench.masters_out[0].ar.arid[4] top.bench.masters_out[0].ar.arid[3] top.bench.masters_out[0].ar.arid[2] top.bench.masters_out[0].ar.arid[1] top.bench.masters_out[0].ar.arid[0]
+@28
+top.bench.masters_out[0].ar.arvalid
+top.bench.masters_in[0].ar.arready
+[pattern_trace] 1
+[pattern_trace] 0