36 lines
881 B
VHDL
36 lines
881 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- "work" denotes the curent library. Similar to this in C++, C# etc...
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use work.axi3intercon_pkg.all;
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entity axi3intercon is
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generic(
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constant MASTER_COUNT : natural := 1;
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constant SLAVE_COUNT : natural := 1
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);
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port(
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aclk : in std_logic;
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aresetn : in std_logic;
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masters_in : out axi_masters_in(0 to MASTER_COUNT - 1);
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masters_out : in axi_masters_out(0 to MASTER_COUNT - 1);
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slaves_in : out axi_masters_in(0 to SLAVE_COUNT - 1);
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slaves_out : in axi_masters_out(0 to SLAVE_COUNT - 1)
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);
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end entity axi3intercon;
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architecture RTL of axi3intercon is
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signal rst : std_logic;
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begin
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reset_sync : process(aclk, aresetn) is
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begin
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if aresetn = '0' then
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rst <= '1';
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elsif rising_edge(aclk) then
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rst <= '0';
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end if;
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end process reset_sync;
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end architecture RTL;
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