fpga/axi3-interconnect
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1ce3f9c97b
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2 Commits

Author SHA1 Message Date
Mario Hüttel
1ce3f9c97b Add simulation for toplevel 2020-03-10 20:06:17 +01:00
Mario Hüttel
79d90c19f0 Add object dolder in simulation 2019-07-26 23:50:05 +02:00