axi3-interconnect/src/axi3-interconnect.vhd

library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- "work" denotes the curent library. Similar to this in C++, C# etc...
use work.axi3intercon_pkg.all;

entity axi3intercon is
	generic(
		constant MASTER_COUNT : natural := 1;
		constant SLAVE_COUNT  : natural := 1
	);
	port(
		aclk        : in  std_logic;
		aresetn     : in  std_logic;
		masters_in  : out axi_masters_in(0 to MASTER_COUNT - 1);
		masters_out : in  axi_masters_out(0 to MASTER_COUNT - 1);
		slaves_in   : out axi_masters_in(0 to SLAVE_COUNT - 1);
		slaves_out  : in  axi_masters_out(0 to SLAVE_COUNT - 1)
	);
end entity axi3intercon;

architecture RTL of axi3intercon is
	signal rst : std_logic;
begin
	reset_sync : process(aclk, aresetn) is
	begin
		if aresetn = '0' then
			rst <= '1';
		elsif rising_edge(aclk) then
			rst <= '0';
		end if;
	end process reset_sync;

end architecture RTL;