fpga/axi3-interconnect
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Mario Hüttel 86d36b6e4a wrote w router
2016-08-22 19:41:10 +02:00
.settings
started type definitions
2016-08-20 14:43:06 +02:00
src
wrote w router
2016-08-22 19:41:10 +02:00
.gitignore
started type definitions
2016-08-20 14:43:06 +02:00
.library_mapping.xml
remove package body, changed aliases to subtypes
2016-08-20 18:08:38 +02:00
.project
started type definitions
2016-08-20 14:43:06 +02:00
Description
AXI3 crossbar interconnect
64 KiB
Languages
VHDL 99.3%
Shell 0.7%