83 lines
3.0 KiB
VHDL
83 lines
3.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.axi3intercon_pkg.all;
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use work.axi_ar_router_pkg.all;
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entity axi3intercon_ar_router is
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port(
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aclk : in std_logic;
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rst : in std_logic;
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masters_out : in axi_ar_masters_out_t(0 to MASTER_COUNT - 1);
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masters_in : out axi_ar_masters_in_t(0 to MASTER_COUNT - 1);
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slaves_out : in axi_ar_slaves_out_t(0 to SLAVE_COUNT);
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slaves_in : out axi_ar_slaves_in_t(0 to SLAVE_COUNT);
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address_array : in axi_slave_addresses_t(0 to SLAVE_COUNT - 1);
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mask_array : in axi_slave_addresses_t(0 to SLAVE_COUNT - 1)
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);
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end entity axi3intercon_ar_router;
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architecture RTL of axi3intercon_ar_router is
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alias clk is aclk;
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type ar_state_t is (AR_READY, AR_ACTIVE);
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type ar_states_t is array (0 to MASTER_COUNT - 1) of ar_state_t;
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signal ar_states : ar_states_t;
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signal arready_s : std_logic_vector(0 to MASTER_COUNT - 1);
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type slave_indexes_t is array (0 to MASTER_COUNT - 1) of integer range 0 to SLAVE_COUNT;
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begin
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arready_gen : for i in 0 to MASTER_COUNT - 1 generate
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masters_in(i).arready <= arready_s(i);
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end generate arready_gen;
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ar_router : process(clk, rst) is
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variable slave_idx : slave_indexes_t;
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variable slave_in_use : std_logic_vector(0 to SLAVE_COUNT);
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begin
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if rst = '1' then
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for i in 0 to MASTER_COUNT - 1 loop
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ar_states(i) <= AR_READY;
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end loop;
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for i in 0 to SLAVE_COUNT loop
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slaves_in(i).arvalid <= '0';
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end loop;
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slave_in_use := (others => '0');
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arready_s <= (others => '1');
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elsif rising_edge(clk) then
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for i in 0 to MASTER_COUNT - 1 loop -- Loop for every master
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case ar_states(i) is
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when AR_READY =>
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arready_s(i) <= '1';
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if masters_out(i).arvalid = '1' and arready_s(i) = '1' then
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slave_idx(i) := calculate_slave(masters_out(i).araddr, address_array, mask_array);
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if slave_in_use(slave_idx(i)) /= '1' then
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slave_in_use(slave_idx(i)) := '1';
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masters_in(i).arready <= '0';
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-- Write request to slave
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slaves_in(slave_idx(i)).araddr <= masters_out(i).araddr;
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slaves_in(slave_idx(i)).arid <= std_logic_vector(to_unsigned(i, WID_SLAVE_BITS - WID_MASTER_BITS)) & masters_out(i).arid;
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slaves_in(slave_idx(i)).arburst <= masters_out(i).arburst;
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slaves_in(slave_idx(i)).arcache <= masters_out(i).arcache;
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slaves_in(slave_idx(i)).arlen <= masters_out(i).arlen;
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slaves_in(slave_idx(i)).arlock <= masters_out(i).arlock;
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slaves_in(slave_idx(i)).arprot <= masters_out(i).arprot;
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slaves_in(slave_idx(i)).arsize <= masters_out(i).arsize;
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slaves_in(slave_idx(i)).arvalid <= '1';
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ar_states(i) <= AR_ACTIVE;
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end if;
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end if;
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when AR_ACTIVE =>
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if slaves_out(slave_idx(i)).arready = '1' then
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slaves_in(slave_idx(i)).arvalid <= '0';
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ar_states(i) <= AR_READY;
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slave_in_use(slave_idx(i)) := '0';
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end if;
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end case;
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end loop;
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end if;
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end process ar_router;
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end architecture RTL;
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