fpga/ws2812b-eth
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reset-sync

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This commit is contained in:
Mario Hüttel
2018-04-07 19:12:55 +02:00
parent c909e0c703
commit 0425710537
1 changed files with 19 additions and 9 deletions
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12
top.vhd
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@@ -88,7 +88,17 @@ architecture RTL of top is
begin -- architecture RTL begin -- architecture RTL
rst <= not rst_hw; reset_sync : process(clk, rst_hw) is
begin
if rst_hw = '0' then
rst <= '1';
elsif rising_edge(clk) then
if rst_hw = '1' then
rst <= '0';
end if;
end if;
end process reset_sync;
smi_1 : entity work.smi smi_1 : entity work.smi
generic map ( generic map (