fpga/ws2812b-eth
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reset-sync

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This commit is contained in:
Mario Hüttel 2018-04-07 19:12:55 +02:00
parent c909e0c703
commit 0425710537
1 changed files with 19 additions and 9 deletions
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26
top.vhd
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@ -36,9 +36,9 @@ entity top is
end entity top; end entity top;
architecture RTL of top is architecture RTL of top is
constant DELAYCNTVAL : integer := 100000; -- set to low value for constant DELAYCNTVAL : integer := 100000; -- set to low value for
-- simulation -- simulation
constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00"; constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
type smi_state_t is (IDLE, STROBE); type smi_state_t is (IDLE, STROBE);
type smi_init_state_t is (SMI_POR, RESET, INIT, DELAY, INIT_COMPLETE); type smi_init_state_t is (SMI_POR, RESET, INIT, DELAY, INIT_COMPLETE);
@ -88,7 +88,17 @@ architecture RTL of top is
begin -- architecture RTL begin -- architecture RTL
rst <= not rst_hw; reset_sync : process(clk, rst_hw) is
begin
if rst_hw = '0' then
rst <= '1';
elsif rising_edge(clk) then
if rst_hw = '1' then
rst <= '0';
end if;
end if;
end process reset_sync;
smi_1 : entity work.smi smi_1 : entity work.smi
generic map ( generic map (
@ -198,12 +208,12 @@ begin -- architecture RTL
case initstate is case initstate is
when SMI_POR => when SMI_POR =>
after_delay_state <= RESET; after_delay_state <= RESET;
delaycounter <= (others => '0'); delaycounter <= (others => '0');
initstate <= DELAY; initstate <= DELAY;
when RESET => when RESET =>
after_delay_state <= INIT; after_delay_state <= INIT;
delaycounter <= (others => '0'); delaycounter <= (others => '0');
sendsmi((others => '0'), x"8000", DELAY); sendsmi((others => '0'), x"8000", DELAY);
when DELAY => when DELAY =>
delaycounter <= delaycounter + 1; delaycounter <= delaycounter + 1;