|
|
93ae71bcbc
|
Add programming files for FTDI EEPROM
|
2021-06-20 12:37:04 +02:00 |
|
|
|
5dba0f8e2d
|
Perform final DRC and generate gerbers for v1.0
v1.0
|
2021-05-25 22:58:09 +02:00 |
|
|
|
4d5ea12e7e
|
Length match RS485 (Yeah... I know its's not necessary. But it looks cool, right?)
|
2021-05-24 02:38:08 +02:00 |
|
|
|
1387a0985b
|
Fix silkscreen
|
2021-05-22 22:21:55 +02:00 |
|
|
|
0523f0c751
|
Finalize layout
|
2021-05-22 22:12:36 +02:00 |
|
|
|
0f977f2eaa
|
Change switch
|
2021-05-22 22:03:39 +02:00 |
|
|
|
34d2778601
|
Fix #6: Remove unnecessary caps
|
2021-05-22 21:46:37 +02:00 |
|
|
|
7bda3e7e27
|
Fix #3: Add Ployfuse with 500 mA to 5V supply
|
2021-05-22 21:41:03 +02:00 |
|
|
|
1cd1b5138b
|
Fix #7
|
2021-05-22 21:23:03 +02:00 |
|
|
|
b86ef7a4cc
|
slighly move a trace to make via fully enclosed in GND plane
|
2021-05-16 21:19:38 +02:00 |
|
|
|
e8315448dd
|
Add possibility to supply target from JTAG input port Pin 19 (JLink can supply 5V on that pin)
|
2021-05-16 21:18:05 +02:00 |
|
|
|
939c3683e8
|
Rename nets and round PCB corners
|
2021-05-16 17:51:57 +02:00 |
|
|
|
2f1fa13ae1
|
Add labeling for git repository
|
2021-05-16 17:38:34 +02:00 |
|
|
|
c453f96bdb
|
First draft. Correct labeling still missing
|
2021-05-16 17:36:18 +02:00 |
|
