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5dba0f8e2d
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Perform final DRC and generate gerbers for v1.0
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2021-05-25 22:58:09 +02:00 |
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4d5ea12e7e
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Length match RS485 (Yeah... I know its's not necessary. But it looks cool, right?)
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2021-05-24 02:38:08 +02:00 |
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1387a0985b
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Fix silkscreen
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2021-05-22 22:21:55 +02:00 |
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0523f0c751
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Finalize layout
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2021-05-22 22:12:36 +02:00 |
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0f977f2eaa
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Change switch
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2021-05-22 22:03:39 +02:00 |
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34d2778601
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Fix #6: Remove unnecessary caps
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2021-05-22 21:46:37 +02:00 |
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7bda3e7e27
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Fix #3: Add Ployfuse with 500 mA to 5V supply
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2021-05-22 21:41:03 +02:00 |
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1cd1b5138b
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Fix #7
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2021-05-22 21:23:03 +02:00 |
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b86ef7a4cc
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slighly move a trace to make via fully enclosed in GND plane
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2021-05-16 21:19:38 +02:00 |
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e8315448dd
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Add possibility to supply target from JTAG input port Pin 19 (JLink can supply 5V on that pin)
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2021-05-16 21:18:05 +02:00 |
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939c3683e8
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Rename nets and round PCB corners
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2021-05-16 17:51:57 +02:00 |
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2f1fa13ae1
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Add labeling for git repository
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2021-05-16 17:38:34 +02:00 |
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c453f96bdb
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First draft. Correct labeling still missing
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2021-05-16 17:36:18 +02:00 |
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