Mario Hüttel mhu
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mhu pushed to master at fpga/ws2812b-demo 2016-10-24 00:06:43 +02:00
5bdf863277 Demo Code for WS2812b LEDs created
mhu pushed to master at mhu/stm32f4-sdio 2016-09-27 17:41:26 +02:00
1844e46167 fixed clock switch
mhu pushed to master at mhu/stm32f4-sdio 2016-09-27 17:33:37 +02:00
9bce46516a implemented clock switch
mhu pushed to master at mhu/stm32f4-sdio 2016-09-27 15:21:25 +02:00
1004efa300 Moved insertion check and write protection check to functions.
mhu pushed to master at mhu/stm32f4-sdio 2016-09-25 19:58:49 +02:00
9c8eb5cc41 fix rtc
mhu pushed to master at mhu/stm32f4-sdio 2016-09-25 19:50:46 +02:00
2e52153b23 Added todos
mhu pushed to master at mhu/stm32f4-sdio 2016-09-25 19:34:16 +02:00
6db78f07c2 implemented initialization
mhu closed issue mhu/stm32f4-sdio#1 2016-08-25 19:38:25 +02:00
User Interface
mhu opened issue mhu/stm32f4-sdio#1 2016-08-25 19:38:10 +02:00
User Interface
mhu pushed to master at mhu/stm32f4-sdio 2016-08-24 21:15:42 +02:00
19655b7259 fixed Makefile
mhu pushed to master at fpga/axi3-interconnect 2016-08-23 22:16:55 +02:00
2359f43ae9 optimized decerr slave
mhu pushed to master at fpga/axi3-interconnect 2016-08-23 22:10:31 +02:00
5ff411a66d fixed copy/paste error
mhu pushed to master at fpga/axi3-interconnect 2016-08-23 22:08:43 +02:00
ccc183c609 wrote decerr slave, ready for testing the functionality of the crossbar
mhu pushed to master at fpga/axi3-interconnect 2016-08-23 18:43:30 +02:00
8ebb16e4d8 started default slave that is accessed on decerr, write read error
mhu pushed to master at fpga/axi3-interconnect 2016-08-23 17:57:47 +02:00
3d7b14c6ff address to slave is now masked
mhu pushed to master at fpga/axi3-interconnect 2016-08-23 17:51:13 +02:00
4ee6195c4d added resets for all signals, wrote b router
mhu pushed to master at fpga/axi3-interconnect 2016-08-22 20:44:34 +02:00
42e475d41f fixed major error in aw and ar router. wrote r router
mhu pushed to master at fpga/axi3-interconnect 2016-08-22 19:43:10 +02:00
9797912af8 moved existing routers in master2slave
mhu pushed to master at fpga/axi3-interconnect 2016-08-22 19:41:01 +02:00
86d36b6e4a wrote w router
mhu pushed to master at fpga/axi3-interconnect 2016-08-21 23:39:45 +02:00
3607ba3842 instantiated ar router and connected it