Mario Hüttel

mhu pushed to master at fpga/axi3-interconnect

2016-08-23 22:16:55 +02:00

2359f43ae9 optimized decerr slave

mhu pushed to master at fpga/axi3-interconnect

2016-08-23 22:10:31 +02:00

5ff411a66d fixed copy/paste error

mhu pushed to master at fpga/axi3-interconnect

2016-08-23 22:08:43 +02:00

ccc183c609 wrote decerr slave, ready for testing the functionality of the crossbar

mhu pushed to master at fpga/axi3-interconnect

2016-08-23 18:43:30 +02:00

8ebb16e4d8 started default slave that is accessed on decerr, write read error

mhu pushed to master at fpga/axi3-interconnect

2016-08-23 17:57:47 +02:00

3d7b14c6ff address to slave is now masked

mhu pushed to master at fpga/axi3-interconnect

2016-08-23 17:51:13 +02:00

4ee6195c4d added resets for all signals, wrote b router

mhu pushed to master at fpga/axi3-interconnect

2016-08-22 20:44:34 +02:00

42e475d41f fixed major error in aw and ar router. wrote r router

mhu pushed to master at fpga/axi3-interconnect

2016-08-22 19:43:10 +02:00

9797912af8 moved existing routers in master2slave

mhu pushed to master at fpga/axi3-interconnect

2016-08-22 19:41:01 +02:00

86d36b6e4a wrote w router

mhu pushed to master at fpga/axi3-interconnect

2016-08-21 23:39:45 +02:00

3607ba3842 instantiated ar router and connected it

mhu pushed to master at fpga/axi3-interconnect

2016-08-21 23:31:02 +02:00

8bd0e57738 fixed ID concatenation

mhu pushed to master at fpga/axi3-interconnect

2016-08-21 20:53:51 +02:00

c660af5df0 fixed aw router to fut VHDL93

mhu pushed to master at fpga/axi3-interconnect

2016-08-21 20:43:51 +02:00

d272ed687b ar router, aw router fixed

mhu pushed to master at fpga/axi3-interconnect

2016-08-21 18:51:57 +02:00

cc9223d089 wrote aw router (untested).

mhu pushed to master at fpga/axi3-interconnect

2016-08-21 17:52:18 +02:00

212cbcac26 added address and mask arrays to aw rounter. aw router started

mhu pushed to master at fpga/axi3-interconnect

2016-08-21 15:40:55 +02:00

438c23290e fixed entity name of aw router

mhu pushed to master at fpga/axi3-interconnect

2016-08-21 15:37:21 +02:00

73c1db7798 modified types to *_t, aw router created and connected

mhu pushed to master at fpga/axi3-interconnect

2016-08-21 14:30:14 +02:00

6aaf75421a finished types. wrote top-entity

mhu pushed to master at fpga/axi3-interconnect

2016-08-20 18:08:23 +02:00

772ccc0da8 remove package body, changed aliases to subtypes

mhu created repository mhu/model-ghdl

2016-08-11 14:53:59 +02:00