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19ae8bce67
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fixed msel pin bug
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2017-01-11 10:49:59 +01:00 |
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2bd138ba01
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added 3d model to footprint of power coil
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2017-01-10 14:04:53 +01:00 |
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41e33910d6
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added vias in power supply for TFP401
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2017-01-08 21:59:38 +01:00 |
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9a04fc70b8
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improved layout
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2017-01-08 21:45:05 +01:00 |
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202c925e6e
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redone switching regulator
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2017-01-08 21:31:00 +01:00 |
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65db531300
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removed track
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2017-01-08 14:01:30 +01:00 |
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4d9c0971b2
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added version number to pcb
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2017-01-08 13:58:48 +01:00 |
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8561e71ad7
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remove 5V output, increased input voltage to 9V+ because regulator is not stable with 5V in
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2017-01-08 13:57:38 +01:00 |
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f45251d2d0
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added cap in PVDD/OVDD of TFP401
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2017-01-07 00:20:38 +01:00 |
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181ea5802a
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moved input cap to bottom layer, improve routing of +2V5
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2017-01-06 18:13:02 +01:00 |
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7e5fce5379
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moved footprints, checked silkscreen positions, reinforced some power tracks
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2017-01-06 16:29:37 +01:00 |
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23596b6827
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improved layout
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2017-01-05 23:21:58 +01:00 |
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a163647422
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exchanged ceramic caps with tantal
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2017-01-05 21:41:36 +01:00 |
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ad263474a2
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fixed GND connection of cap for regulator
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2017-01-05 20:07:08 +01:00 |
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ab8a7ae856
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fixed routing, moved caps to bottom layer, added caps for 5V rail
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2017-01-04 21:32:46 +01:00 |
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716c1b88e5
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fixed cap in VIO for FPGA, added project/my name and date
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2017-01-04 03:07:54 +01:00 |
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マリオ
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9b88a8374f
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fixed unconnected pin
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2017-01-03 15:28:50 +01:00 |
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e92f1b571f
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improve GND plane for switching regulator
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2017-01-03 00:32:33 +01:00 |
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71dffbb622
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fixed routing of some tracks
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2017-01-02 21:39:35 +01:00 |
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91d4946fd7
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fixed copper pour
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2017-01-01 23:15:30 +01:00 |
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032c2f39c6
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edited
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2017-01-01 23:05:09 +01:00 |
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e1a0819a87
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created gerber
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2017-01-01 21:12:58 +01:00 |
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0a8f8143bf
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added gerber files to gitignore
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2017-01-01 20:45:27 +01:00 |
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84a264b12b
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changed copper pur
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2017-01-01 20:43:55 +01:00 |
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d94a5e72cb
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added symbols, fixed silkscreen, last changes
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2017-01-01 20:34:59 +01:00 |
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78cc0cddcd
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edited polygons
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2016-12-17 22:40:00 +01:00 |
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5395223a8b
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edited layout
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2016-12-13 20:55:46 +01:00 |
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684f9625ee
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finished first draft
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2016-12-13 20:25:47 +01:00 |
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8fd8d39297
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layout, added cap in 3v3
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2016-12-13 15:31:47 +01:00 |
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5dfb6d97ed
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epcs fixed
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2016-12-13 11:56:05 +01:00 |
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e20c479d28
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changed schematic, routed
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2016-12-13 11:47:49 +01:00 |
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0f1c797639
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layouted supplies for fpga
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2016-12-12 22:12:52 +01:00 |
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0caa103ee5
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fixed schematic, routed foo
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2016-12-12 21:04:51 +01:00 |
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2541362c90
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GND routing
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2016-12-12 19:26:53 +01:00 |
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7825d0ca32
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fixed schematic errors, layouted power supply, fixed dvi in and out
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2016-12-12 19:16:34 +01:00 |
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d239229656
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fixed lengths, positioned dvi ports correctly
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2016-12-12 11:23:06 +01:00 |
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66eda104d0
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flipped chips, removed termination in DVI-out
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2016-12-11 21:31:14 +01:00 |
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b733c4108e
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flipped resistor arrays, started layout
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2016-12-11 18:30:16 +01:00 |
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1ebe08323d
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finished component association
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2016-12-11 17:37:27 +01:00 |
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68374bbb30
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unified rsistor array sizes, associated components
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2016-12-10 16:58:19 +01:00 |
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4c4b95c8d3
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changed transistors for level shifting, started footprint association
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2016-12-09 21:21:27 +01:00 |
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df684d3788
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annotated schematic
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2016-12-09 20:32:01 +01:00 |
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200b8e1a0b
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finished schematic
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2016-12-09 20:28:56 +01:00 |
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f0479ce996
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reduced txclock to single ended, connected power down
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2016-12-07 20:29:10 +01:00 |
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124ed27ef7
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toplevel connection DVI out, i2c level shifter
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2016-12-07 17:40:21 +01:00 |
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522cee0947
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moved things
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2016-12-07 16:36:46 +01:00 |
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280f4e7cea
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DVI out edited
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2016-12-07 14:58:40 +01:00 |
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a4a2688857
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added termination resistors, powersupply for tfp 410, dvi out connector
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2016-12-07 11:03:18 +01:00 |
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ac2853d348
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changed value for termination resistors
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2016-12-05 21:09:45 +01:00 |
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634286fcc8
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used resistor arrays instead of individual resistors
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2016-12-05 21:00:29 +01:00 |
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