65 Commits

Author SHA1 Message Date
42661014f7 Updated 2018-12-09 23:05:47 +01:00
5a3367d7df added mounting holes 2017-01-22 19:56:58 +01:00
6dc8299d9d recalculated copper pours 2017-01-22 18:41:35 +01:00
7e9ff67ad6 changed GND copper pours on top layer 2017-01-22 18:41:07 +01:00
c57e20a71c improved layout 2017-01-22 18:27:37 +01:00
c0b47089c5 connected HDMI housing to GND, increased copper pour cclearance on outer layers 2017-01-22 18:02:11 +01:00
0ab286277b added 3d model to hdmi connectors 2017-01-22 17:51:31 +01:00
adcb45e3f3 routed foo, replaced DVI with HDMI 2017-01-22 17:45:48 +01:00
e4bc30bf46 Everything connected, ready for improving layout 2017-01-21 17:44:52 +01:00
07f4bc1c3c layoutet power supply 2017-01-21 00:02:07 +01:00
7949d16df1 routed vio,1v2 2017-01-20 21:17:12 +01:00
cff2d16bbb layouted 2017-01-20 20:08:14 +01:00
e7ae749bc4 copper pour 2017-01-14 18:14:15 +01:00
05c4b58513 moved down power circuitry 2017-01-14 18:07:13 +01:00
24bdf7ae00 remove resistor network for TFP410, layoutet databus of TFP410, startet with bus from TFP401 2017-01-14 17:56:21 +01:00
ca0aabd1f4 fixed component-footprint assosciation, routed some power realted stuff, routed DVI 2017-01-14 16:46:18 +01:00
64f8fe6f11 Picked inductor, Footprint association finished 2017-01-14 01:41:19 +01:00
6d765ac5d2 created board 2017-01-14 01:03:28 +01:00
eccf90a93c started version 2,changed power supply, included latest fixes 2017-01-13 23:46:44 +01:00
a2f2ddae38 fixed footprints (added soldermask), increased clearance of copper pour on top and bottom 2017-01-11 21:14:27 +01:00
b4d73d8834 improved pcb 2017-01-11 19:53:08 +01:00
027cc8c141 removed resistors for configuration, reannotated whole schematic 2017-01-11 14:43:32 +01:00
19ae8bce67 fixed msel pin bug 2017-01-11 10:49:59 +01:00
2bd138ba01 added 3d model to footprint of power coil 2017-01-10 14:04:53 +01:00
41e33910d6 added vias in power supply for TFP401 2017-01-08 21:59:38 +01:00
9a04fc70b8 improved layout 2017-01-08 21:45:05 +01:00
202c925e6e redone switching regulator 2017-01-08 21:31:00 +01:00
65db531300 removed track 2017-01-08 14:01:30 +01:00
4d9c0971b2 added version number to pcb 2017-01-08 13:58:48 +01:00
8561e71ad7 remove 5V output, increased input voltage to 9V+ because regulator is not stable with 5V in 2017-01-08 13:57:38 +01:00
f45251d2d0 added cap in PVDD/OVDD of TFP401 2017-01-07 00:20:38 +01:00
181ea5802a moved input cap to bottom layer, improve routing of +2V5 2017-01-06 18:13:02 +01:00
7e5fce5379 moved footprints, checked silkscreen positions, reinforced some power tracks 2017-01-06 16:29:37 +01:00
23596b6827 improved layout 2017-01-05 23:21:58 +01:00
a163647422 exchanged ceramic caps with tantal 2017-01-05 21:41:36 +01:00
ad263474a2 fixed GND connection of cap for regulator 2017-01-05 20:07:08 +01:00
ab8a7ae856 fixed routing, moved caps to bottom layer, added caps for 5V rail 2017-01-04 21:32:46 +01:00
716c1b88e5 fixed cap in VIO for FPGA, added project/my name and date 2017-01-04 03:07:54 +01:00
マリオ
9b88a8374f fixed unconnected pin 2017-01-03 15:28:50 +01:00
e92f1b571f improve GND plane for switching regulator 2017-01-03 00:32:33 +01:00
71dffbb622 fixed routing of some tracks 2017-01-02 21:39:35 +01:00
91d4946fd7 fixed copper pour 2017-01-01 23:15:30 +01:00
032c2f39c6 edited 2017-01-01 23:05:09 +01:00
e1a0819a87 created gerber 2017-01-01 21:12:58 +01:00
0a8f8143bf added gerber files to gitignore 2017-01-01 20:45:27 +01:00
84a264b12b changed copper pur 2017-01-01 20:43:55 +01:00
d94a5e72cb added symbols, fixed silkscreen, last changes 2017-01-01 20:34:59 +01:00
78cc0cddcd edited polygons 2016-12-17 22:40:00 +01:00
5395223a8b edited layout 2016-12-13 20:55:46 +01:00
684f9625ee finished first draft 2016-12-13 20:25:47 +01:00
8fd8d39297 layout, added cap in 3v3 2016-12-13 15:31:47 +01:00
5dfb6d97ed epcs fixed 2016-12-13 11:56:05 +01:00
e20c479d28 changed schematic, routed 2016-12-13 11:47:49 +01:00
0f1c797639 layouted supplies for fpga 2016-12-12 22:12:52 +01:00
0caa103ee5 fixed schematic, routed foo 2016-12-12 21:04:51 +01:00
2541362c90 GND routing 2016-12-12 19:26:53 +01:00
7825d0ca32 fixed schematic errors, layouted power supply, fixed dvi in and out 2016-12-12 19:16:34 +01:00
d239229656 fixed lengths, positioned dvi ports correctly 2016-12-12 11:23:06 +01:00
66eda104d0 flipped chips, removed termination in DVI-out 2016-12-11 21:31:14 +01:00
b733c4108e flipped resistor arrays, started layout 2016-12-11 18:30:16 +01:00
1ebe08323d finished component association 2016-12-11 17:37:27 +01:00
68374bbb30 unified rsistor array sizes, associated components 2016-12-10 16:58:19 +01:00
4c4b95c8d3 changed transistors for level shifting, started footprint association 2016-12-09 21:21:27 +01:00
df684d3788 annotated schematic 2016-12-09 20:32:01 +01:00
200b8e1a0b finished schematic 2016-12-09 20:28:56 +01:00
15 changed files with 22824 additions and 2769 deletions

3
.gitignore vendored
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@@ -3,4 +3,5 @@
*.kicad_pcb-bak
_saved*
_autosave*
gerber
rescue-backup

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914
dvi-sniffer-rescue.lib Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# +1V2
#
DEF +1V2 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "+1V2" 0 140 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +1V2 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# +2V5
#
DEF +2V5 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "+2V5" 0 140 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +2V5 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# +3V3
#
DEF +3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "+3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# +5V
#
DEF +5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# +V_IO
#
DEF +V_IO #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "+V_IO" 0 140 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +V_IO 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# AP111725
#
DEF AP111725 U 0 30 Y Y 1 F N
F0 "U" 100 -250 50 H V C CNN
F1 "AP111725" 0 250 50 H V C CNN
F2 "TO_SOT_Packages_SMD:SOT-223" 0 -350 50 H I C CNN
F3 "" 100 -250 50 H V C CNN
$FPLIST
SOT-223*
$ENDFPLIST
DRAW
S -200 -200 200 200 0 1 10 f
X GND/ADJ 1 0 -300 100 U 50 50 1 1 W
X VO 2 300 0 100 L 50 50 1 1 w
X VI 3 -300 0 100 R 50 50 1 1 W
X VO 4 300 0 100 L 50 50 1 1 w N
ENDDRAW
ENDDEF
#
# BARREL_JACK
#
DEF BARREL_JACK CON 0 40 Y Y 1 F N
F0 "CON" 0 250 50 H V C CNN
F1 "BARREL_JACK" 0 -200 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
A -300 99 49 -900 1788 0 1 0 N -300 50 -350 100
A -300 101 49 900 -1788 0 1 0 N -300 150 -350 100
S 100 150 0 50 0 1 0 N
P 2 0 1 0 -300 50 0 50 N
P 2 0 1 0 0 150 -300 150 N
P 3 0 1 0 100 0 -50 0 -50 -100 N
P 5 0 1 0 100 -100 -150 -100 -200 -50 -250 -100 -350 -100 N
X ~ 1 300 100 200 L 50 50 1 1 P
X ~ 2 300 -100 200 L 50 50 1 1 P
X ~ 3 300 0 200 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# C
#
DEF C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
C?
C_????_*
C_????
SMD*_c
Capacitor*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_01X10
#
DEF CONN_01X10 P 0 40 Y N 1 F N
F0 "P" 0 550 50 H V C CNN
F1 "CONN_01X10" 100 0 50 V V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
Pin_Header_Straight_1X10
Pin_Header_Angled_1X10
Socket_Strip_Straight_1X10
Socket_Strip_Angled_1X10
$ENDFPLIST
DRAW
S -50 -445 10 -455 0 1 0 N
S -50 -345 10 -355 0 1 0 N
S -50 -245 10 -255 0 1 0 N
S -50 -145 10 -155 0 1 0 N
S -50 -45 10 -55 0 1 0 N
S -50 55 10 45 0 1 0 N
S -50 155 10 145 0 1 0 N
S -50 255 10 245 0 1 0 N
S -50 355 10 345 0 1 0 N
S -50 455 10 445 0 1 0 N
S -50 500 50 -500 0 1 0 N
X P1 1 -200 450 150 R 50 50 1 1 P
X P10 10 -200 -450 150 R 50 50 1 1 P
X P2 2 -200 350 150 R 50 50 1 1 P
X P3 3 -200 250 150 R 50 50 1 1 P
X P4 4 -200 150 150 R 50 50 1 1 P
X P5 5 -200 50 150 R 50 50 1 1 P
X P6 6 -200 -50 150 R 50 50 1 1 P
X P7 7 -200 -150 150 R 50 50 1 1 P
X P8 8 -200 -250 150 R 50 50 1 1 P
X P9 9 -200 -350 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_02X05
#
DEF CONN_02X05 P 0 1 Y N 1 F N
F0 "P" 0 300 50 H V C CNN
F1 "CONN_02X05" 0 -300 50 H V C CNN
F2 "" 0 -1200 50 H V C CNN
F3 "" 0 -1200 50 H V C CNN
$FPLIST
Pin_Header_Straight_2X05
Pin_Header_Angled_2X05
Socket_Strip_Straight_2X05
Socket_Strip_Angled_2X05
$ENDFPLIST
DRAW
S -100 -195 -50 -205 0 1 0 N
S -100 -95 -50 -105 0 1 0 N
S -100 5 -50 -5 0 1 0 N
S -100 105 -50 95 0 1 0 N
S -100 205 -50 195 0 1 0 N
S -100 250 100 -250 0 1 0 N
S 50 -195 100 -205 0 1 0 N
S 50 -95 100 -105 0 1 0 N
S 50 5 100 -5 0 1 0 N
S 50 105 100 95 0 1 0 N
S 50 205 100 195 0 1 0 N
X P1 1 -250 200 150 R 50 50 1 1 P
X P10 10 250 -200 150 L 50 50 1 1 P
X P2 2 250 200 150 L 50 50 1 1 P
X P3 3 -250 100 150 R 50 50 1 1 P
X P4 4 250 100 150 L 50 50 1 1 P
X P5 5 -250 0 150 R 50 50 1 1 P
X P6 6 250 0 150 L 50 50 1 1 P
X P7 7 -250 -100 150 R 50 50 1 1 P
X P8 8 250 -100 150 L 50 50 1 1 P
X P9 9 -250 -200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CP
#
DEF CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
CP*
C_Axial*
C_Radial*
TantalC*
C*elec
c_elec*
SMD*_Pol
$ENDFPLIST
DRAW
S -90 20 -90 40 0 1 0 N
S -90 20 90 20 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
S 90 40 -90 40 0 1 0 N
S 90 40 90 20 0 1 0 N
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# EP4CE6E22C8N
#
DEF EP4CE6E22C8N U 0 40 Y Y 10 L N
F0 "U" 100 -100 60 H V C CNN
F1 "EP4CE6E22C8N" 600 -100 60 H V C CNN
F2 "" 0 -50 60 H V C CNN
F3 "" 0 -50 60 H V C CNN
DRAW
S 0 1700 950 0 1 1 0 f
S 0 1000 1000 0 2 1 0 f
S 0 800 1000 0 3 1 0 f
S 0 1100 1200 0 4 1 0 f
S 0 1400 1000 0 5 1 0 f
S 0 1300 850 0 6 1 0 f
S 0 1000 1200 0 7 1 0 f
S 0 1300 1100 0 8 1 0 f
S 0 1200 1200 0 9 1 0 f
S 0 1350 550 0 10 1 0 f
X VCCINT 102 -200 1150 200 R 50 50 1 1 W
X VCCA2 107 -200 550 200 R 50 50 1 1 W
X GNDA2 108 1150 50 200 L 50 50 1 1 W
X VCCD_PLL2 109 -200 150 200 R 50 50 1 1 W
X VCCINT 116 -200 1050 200 R 50 50 1 1 W
X GND 118 1150 850 200 L 50 50 1 1 W
X GND 123 1150 750 200 L 50 50 1 1 W
X GND 131 1150 650 200 L 50 50 1 1 W
X VCCINT 134 -200 950 200 R 50 50 1 1 W
X GND 140 1150 550 200 L 50 50 1 1 W
X GND 19 1150 1650 200 L 50 50 1 1 W
X GND 22 1150 350 200 L 50 50 1 1 W
X GND 27 1150 1550 200 L 50 50 1 1 W
X VCCINT 29 -200 1550 200 R 50 50 1 1 W
X VCCA1 35 -200 650 200 R 50 50 1 1 W
X GNDA1 36 1150 150 200 L 50 50 1 1 W
X VCCD_PLL1 37 -200 250 200 R 50 50 1 1 W
X GND 4 1150 450 200 L 50 50 1 1 W
X GND 41 1150 1450 200 L 50 50 1 1 W
X VCCINT 45 -200 1450 200 R 50 50 1 1 W
X GND 48 1150 1350 200 L 50 50 1 1 W
X VCCINT 5 -200 1650 200 R 50 50 1 1 W
X GND 57 1150 1250 200 L 50 50 1 1 W
X VCCINT 61 -200 1350 200 R 50 50 1 1 W
X GND 63 1150 1150 200 L 50 50 1 1 W
X VCCINT 78 -200 1250 200 R 50 50 1 1 W
X GND 79 1150 250 200 L 50 50 1 1 W
X GND 82 1150 1050 200 L 50 50 1 1 W
X GND 95 1150 950 200 L 50 50 1 1 W
X B1_IO 1 -200 950 200 R 50 50 2 1 B
X B1_L4p 10 -200 350 200 R 50 50 2 1 B
X B1_L4n 11 -200 250 200 R 50 50 2 1 B
X B1_DATA0 13 -200 150 200 R 50 50 2 1 B
X VCCIO1 17 1200 950 200 L 50 50 2 1 W
X B1_IO 2 -200 850 200 R 50 50 2 1 B
X B1_CLK1_DIFFCLK_0n 23 -200 50 200 R 50 50 2 1 B
X B1_IO 3 -200 750 200 R 50 50 2 1 B
X B1_L1n_ASDO 6 -200 650 200 R 50 50 2 1 W
X B1_VREFB1N0 7 -200 550 200 R 50 50 2 1 B
X B1_L2p_nCSO 8 -200 450 200 R 50 50 2 1 B
X B2CLK2_DIFFCLK_1p 24 -200 750 200 R 50 50 3 1 B
X B2_CLK3_DIFFCLK_1n 25 -200 650 200 R 50 50 3 1 B
X VCCIO2 26 1200 50 200 L 50 50 3 1 W
X B2_DIFFIO_L6n 28 -200 550 200 R 50 50 3 1 B
X B2_DIFFIO_L8p 30 -200 450 200 R 50 50 3 1 B
X B2_VREFB2N0 31 -200 350 200 R 50 50 3 1 B
X B2_RUP1 32 -200 250 200 R 50 50 3 1 B
X B2_RDN1 33 -200 150 200 R 50 50 3 1 B
X B2_IO 34 -200 50 200 R 50 50 3 1 B
X B3_DIFFIO_B1p 38 -200 1050 200 R 50 50 4 1 B
X B3_DIFFIO_B1n 39 -200 950 200 R 50 50 4 1 B
X VCCIO3 40 1400 1050 200 L 50 50 4 1 W
X B3_IO 42 -200 850 200 R 50 50 4 1 B
X B3_PLL1_CLKOUTp 43 -200 750 200 R 50 50 4 1 B
X B3_PLL1_CLKOUTn 44 -200 650 200 R 50 50 4 1 B
X B3_VREFB3N0 46 -200 550 200 R 50 50 4 1 B
X VCCIO3 47 1400 950 200 L 50 50 4 1 W
X B3_DIFFIO_B9p 49 -200 450 200 R 50 50 4 1 B
X B3_DIFFIO_B9n 50 -200 350 200 R 50 50 4 1 B
X B3_DIFFIO_B10p 51 -200 250 200 R 50 50 4 1 B
X B3_DIFFIO_B11p 52 -200 150 200 R 50 50 4 1 B
X B3_DIFFIO_B11n 53 -200 50 200 R 50 50 4 1 B
X B4_DIFFIO_B12p 54 -200 1350 200 R 50 50 5 1 B
X B4_DIFFIO_B12n 55 -200 1250 200 R 50 50 5 1 B
X VCCIO4 56 1200 1350 200 L 50 50 5 1 W
X B4_DIFFIO_B15p 58 -200 1150 200 R 50 50 5 1 B
X B4_DIFFIO_B16p 59 -200 1050 200 R 50 50 5 1 B
X B4_DIFFIO_B16n 60 -200 950 200 R 50 50 5 1 B
X VCCIO4 62 1200 1250 200 L 50 50 5 1 W
X B4_IO 64 -200 850 200 R 50 50 5 1 B
X B4_VREFB4N0 65 -200 750 200 R 50 50 5 1 B
X B4_RUP2 66 -200 650 200 R 50 50 5 1 B
X B4_RDN2 67 -200 550 200 R 50 50 5 1 B
X B4_DIFFIO_B20n 68 -200 450 200 R 50 50 5 1 B
X B4_IO 69 -200 350 200 R 50 50 5 1 B
X B4_DIFFIO_B21p 70 -200 250 200 R 50 50 5 1 B
X B4_DIFFIO_B21n 71 -200 150 200 R 50 50 5 1 B
X B4_DIFFIO_B22p 72 -200 50 200 R 50 50 5 1 B
X B5_IO 73 -200 1250 200 R 50 50 6 1 B
X B5_IO 74 -200 1150 200 R 50 50 6 1 B
X B5_IO 75 -200 1050 200 R 50 50 6 1 B
X B5_RUP3 76 -200 950 200 R 50 50 6 1 B
X B5_RDN3 77 -200 850 200 R 50 50 6 1 B
X B5_VREFB5N0 80 -200 750 200 R 50 50 6 1 B
X VCCIO5 81 1050 1250 200 L 50 50 6 1 W
X B5_IO 83 -200 650 200 R 50 50 6 1 B
X B5_DIFFIO_R8n 84 -200 550 200 R 50 50 6 1 B
X B5_DIFFIO_R8p 85 -200 450 200 R 50 50 6 1 B
X B5_DIFFIO_R7n 86 -200 350 200 R 50 50 6 1 B
X B5_DIFFIO_R7p 87 -200 250 200 R 50 50 6 1 B
X B5_CLK7_DIFFCLK_3n 88 -200 150 200 R 50 50 6 1 B
X B5_CLK6_DIFFCLK_3p 89 -200 50 200 R 50 50 6 1 B
X B6_IO 100 -200 550 200 R 50 50 7 1 B
X B6_DIFFIO_R3n_nCEO 101 -200 450 200 R 50 50 7 1 B
X B6_DIFFIO_R3p_CLKUSR 103 -200 350 200 R 50 50 7 1 B
X B6_IO 104 -200 250 200 R 50 50 7 1 B
X B6_VREFB6N0 105 -200 150 200 R 50 50 7 1 B
X B6_DIFFIO_R1n 106 -200 50 200 R 50 50 7 1 B
X B6_CLK5_DIFFCLK_2n 90 -200 950 200 R 50 50 7 1 B
X B6_CLK4_DIFFCLK_2p 91 -200 850 200 R 50 50 7 1 B
X VCCIO6 93 1400 950 200 L 50 50 7 1 W
X B6_DIFFIO_R4n 98 -200 750 200 R 50 50 7 1 B
X B6_DIFFIO_R4p 99 -200 650 200 R 50 50 7 1 B
X B7_DIFFIO_T20p 110 -200 1250 200 R 50 50 8 1 B
X B7_DIFFIOT19p 111 -200 1150 200 R 50 50 8 1 B
X B7_PLL2_CLKOUTn 112 -200 1050 200 R 50 50 8 1 B
X B7_PLL2_CLKOUTp 113 -200 950 200 R 50 50 8 1 B
X B7_RUP4 114 -200 850 200 R 50 50 8 1 B
X B7_RDN4 115 -200 750 200 R 50 50 8 1 B
X VCCIO7 117 1300 1250 200 L 50 50 8 1 W
X B7_VREFB7N0 119 -200 650 200 R 50 50 8 1 B
X B7_DIFFIO_T16n 120 -200 550 200 R 50 50 8 1 B
X B7_DIFFIO_T16p 121 -200 450 200 R 50 50 8 1 B
X VCCIO7 122 1300 1150 200 L 50 50 8 1 W
X B7_DIFFIO_T13p 124 -200 350 200 R 50 50 8 1 B
X B7_IO 125 -200 250 200 R 50 50 8 1 B
X B7_DIFFIO_T12n 126 -200 150 200 R 50 50 8 1 B
X B7_DIFFIO_T12p 127 -200 50 200 R 50 50 8 1 B
X B8_DIFFIO_T11n 128 -200 1150 200 R 50 50 9 1 B
X B8_DIFFIO_T11p 129 -200 1050 200 R 50 50 9 1 B
X VCCIO8 130 1400 1150 200 L 50 50 9 1 W
X B8_DIFFIO_T10n_DATA2 132 -200 950 200 R 50 50 9 1 B
X B8_DIFFIO_T10p_DATA3 133 -200 850 200 R 50 50 9 1 B
X B8_DIFFIO_T8n 135 -200 750 200 R 50 50 9 1 B
X B8_VREFB8N0 136 -200 650 200 R 50 50 9 1 B
X B8_IO_DATA5 137 -200 550 200 R 50 50 9 1 B
X B8_IO_DATA6 138 -200 450 200 R 50 50 9 1 B
X VCCIO8 139 1400 1050 200 L 50 50 9 1 W
X B8_DIFFIO_T5p 141 -200 350 200 R 50 50 9 1 B
X B8_DIFFIO_T2p 142 -200 250 200 R 50 50 9 1 B
X B8_DIFFIO_T1n 143 -200 150 200 R 50 50 9 1 B
X B8_DIFFIO_T1p 144 -200 50 200 R 50 50 9 1 B
X DCLK 12 -200 750 200 R 50 50 10 1 B C
X nCONFIG 14 -200 650 200 R 50 50 10 1 I
X TDI 15 -200 1200 200 R 50 50 10 1 I
X TCK 16 -200 1300 200 R 50 50 10 1 I C
X TMS 18 -200 1000 200 R 50 50 10 1 I
X TDO 20 -200 1100 200 R 50 50 10 1 O
X nCE 21 -200 550 200 R 50 50 10 1 I
X nSTATUS 9 -200 850 200 R 50 50 10 1 C
X CONF_DONE 92 -200 350 200 R 50 50 10 1 C
X MSEL0 94 -200 250 200 R 50 50 10 1 I
X MSEL1 96 -200 150 200 R 50 50 10 1 I
X MSEL2 97 -200 50 200 R 50 50 10 1 I
ENDDRAW
ENDDEF
#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# HDMI-Jack
#
DEF HDMI-Jack P 0 40 Y Y 1 F N
F0 "P" 600 50 60 H V C CNN
F1 "HDMI-Jack" 250 50 60 H V C CNN
F2 "" 0 0 60 H I C CNN
F3 "" 0 0 60 H I C CNN
DRAW
S 0 0 900 -2500 0 1 0 f
X TMDS2+ 1 -200 -600 200 R 50 50 1 1 I
X TMDSC+ 10 -200 -850 200 R 50 50 1 1 I
X TMDSCS 11 -200 -2450 200 R 50 50 1 1 I
X TMDSC- 12 -200 -950 200 R 50 50 1 1 I
X CEC 13 -200 -1300 200 R 50 50 1 1 I
X ETH/AUDRET/RESV 14 -200 -1950 200 R 50 50 1 1 I
X SCL 15 -200 -1800 200 R 50 50 1 1 I
X SDA 16 -200 -1700 200 R 50 50 1 1 I
X GND 17 -200 -1600 200 R 50 50 1 1 I
X +5V 18 -200 -1500 200 R 50 50 1 1 I
X HOTPLUG 19 -200 -1400 200 R 50 50 1 1 I
X TMDS2S 2 -200 -2350 200 R 50 50 1 1 I
X HOUSING 20 1100 -450 200 L 50 50 1 1 I
X HOUSING 21 1100 -350 200 L 50 50 1 1 I
X HOUSING 22 1100 -250 200 L 50 50 1 1 I
X HOUSING 23 1100 -150 200 L 50 50 1 1 I
X TMDS2- 3 -200 -700 200 R 50 50 1 1 I
X TMDS1+ 4 -200 -350 200 R 50 50 1 1 I
X TMDS1S 5 -200 -2250 200 R 50 50 1 1 I
X TMDS1- 6 -200 -450 200 R 50 50 1 1 I
X TMDS0+ 7 -200 -100 200 R 50 50 1 1 I
X TMDS0S 8 -200 -2150 200 R 50 50 1 1 I
X TMDS0- 9 -200 -200 200 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# LED
#
DEF LED D 0 40 Y N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
LED*
$ENDFPLIST
DRAW
P 2 0 1 8 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 8 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# LTC3612-TSSOP
#
DEF LTC3612-TSSOP U 0 40 Y Y 1 F N
F0 "U" 900 50 60 H V C CNN
F1 "LTC3612-TSSOP" 400 50 60 H V C CNN
F2 "" 0 0 60 H I C CNN
F3 "" 0 0 60 H I C CNN
DRAW
S 0 0 1000 -1200 0 1 0 F
X SVin 1 -200 -50 200 R 50 50 1 1 W
X SGND 10 600 -1400 200 U 50 50 1 1 W
X SW 12 1200 -50 200 L 50 50 1 1 w
X SW 14 1200 -150 200 L 50 50 1 1 w
X PVIN 15 -200 -350 200 R 50 50 1 1 W
X PVIN 16 -200 -250 200 R 50 50 1 1 W
X SW 17 1200 -250 200 L 50 50 1 1 w
X SW 19 1200 -350 200 L 50 50 1 1 w
X RUN 2 -200 -700 200 R 50 50 1 1 I
X PVIN_DRV 20 -200 -150 200 R 50 50 1 1 W
X PGND-Pad 21 500 -1400 200 U 50 50 1 1 W
X PGOOD 3 -200 -500 200 R 50 50 1 1 C
X MODE 4 -200 -800 200 R 50 50 1 1 I
X VFB 5 -200 -900 200 R 50 50 1 1 I
X ITH 6 -200 -1000 200 R 50 50 1 1 I
X TRACK/SS 7 -200 -600 200 R 50 50 1 1 I
X DDR 8 1200 -1050 200 L 50 50 1 1 I
X RT/SYNC 9 -200 -1100 200 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# L_Core_Ferrite_Small
#
DEF L_Core_Ferrite_Small L 0 10 N N 1 F N
F0 "L" 50 40 50 H V L CNN
F1 "L_Core_Ferrite_Small" 50 -50 50 H V L CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
Choke_*
*Coil*
$ENDFPLIST
DRAW
A 0 -60 20 -899 899 0 1 0 N 0 -80 0 -40
A 0 -20 20 -899 899 0 1 0 N 0 -40 0 0
A 0 20 20 -899 899 0 1 0 N 0 0 0 40
A 0 60 20 -899 899 0 1 0 N 0 40 0 80
P 2 0 1 0 30 -75 30 -65 N
P 2 0 1 0 30 -55 30 -45 N
P 2 0 1 0 30 -35 30 -25 N
P 2 0 1 0 30 -15 30 -5 N
P 2 0 1 0 30 5 30 15 N
P 2 0 1 0 30 25 30 35 N
P 2 0 1 0 30 45 30 55 N
P 2 0 1 0 30 65 30 75 N
P 2 0 1 0 40 -65 40 -75 N
P 2 0 1 0 40 -45 40 -55 N
P 2 0 1 0 40 -25 40 -35 N
P 2 0 1 0 40 -5 40 -15 N
P 2 0 1 0 40 15 40 5 N
P 2 0 1 0 40 35 40 25 N
P 2 0 1 0 40 55 40 45 N
P 2 0 1 0 40 75 40 65 N
X ~ 1 0 100 20 D 50 50 1 1 P
X ~ 2 0 -100 20 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# L_Small
#
DEF L_Small L 0 10 N N 1 F N
F0 "L" 30 40 50 H V L CNN
F1 "L_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
Choke_*
*Coil*
$ENDFPLIST
DRAW
A 0 -60 20 -899 899 0 1 0 N 0 -80 0 -40
A 0 -20 20 -899 899 0 1 0 N 0 -40 0 0
A 0 20 20 -899 899 0 1 0 N 0 0 0 40
A 0 60 20 -899 899 0 1 0 N 0 40 0 80
X ~ 1 0 100 20 D 50 50 1 1 P
X ~ 2 0 -100 20 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# M25PX32-VMW
#
DEF M25PX32-VMW U 0 40 Y Y 1 F N
F0 "U" -400 400 50 H V C CNN
F1 "M25PX32-VMW" 300 -400 50 H V C CNN
F2 "Housings_SOIC:SOIJ-8_5.3x5.3mm_Pitch1.27mm" 650 50 50 H I C CNN
F3 "" 150 -100 50 H V C CNN
$FPLIST
SOIJ*5.3x5.3mm*Pitch1.27mm*
$ENDFPLIST
DRAW
S -450 350 450 -350 0 1 10 f
X S# 1 -600 0 150 R 50 50 1 1 I I
X DQ1 2 600 200 150 L 50 50 1 1 B
X W#/VPP 3 -600 -100 150 R 50 50 1 1 I I
X VSS 4 0 -500 150 U 50 50 1 1 W
X DQ0 5 -600 200 150 R 50 50 1 1 B
X C 6 -600 100 150 R 50 50 1 1 I
X HOLD# 7 -600 -200 150 R 50 50 1 1 I I
X VCC 8 0 500 150 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# OSC
#
DEF OSC U 0 40 Y Y 1 F N
F0 "U" 200 -100 60 H V C CNN
F1 "OSC" 600 -100 60 H V C CNN
F2 "" 200 -150 60 H V C CNN
F3 "" 200 -150 60 H V C CNN
DRAW
S 0 0 800 700 1 1 0 N
S 200 360 250 340 1 1 0 N
P 2 1 1 0 190 370 260 370 N
P 2 1 1 0 225 250 225 330 N
P 2 1 1 0 225 450 225 370 N
P 2 1 1 0 260 330 190 330 N
P 2 1 1 0 300 250 225 250 N
P 2 1 1 0 300 450 225 450 N
P 2 1 1 0 575 350 550 350 N
P 3 1 1 0 570 550 440 550 440 420 N
P 4 1 1 0 300 500 300 200 550 350 300 500 N
X CON 1 1100 550 300 L 60 60 1 1 I
X VSS 2 -300 150 300 R 60 60 1 1 W
X OUT 3 1100 350 300 L 60 60 1 1 O
X VDD 4 -300 550 300 R 60 60 1 1 W
ENDDRAW
ENDDEF
#
# Polyfuse
#
DEF Polyfuse F 0 0 N Y 1 F N
F0 "F" -100 0 50 V V C CNN
F1 "Polyfuse" 100 0 50 V V C CNN
F2 "" 50 -200 50 H I L CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
*polyfuse*
*PTC*
$ENDFPLIST
DRAW
S -30 100 30 -100 0 1 10 N
P 2 0 1 0 0 100 0 -100 N
P 4 0 1 0 -60 100 -60 60 60 -60 60 -100 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Q_NMOS_GSD
#
DEF Q_NMOS_GSD Q 0 0 Y N 1 F N
F0 "Q" 200 50 50 H V L CNN
F1 "Q_NMOS_GSD" 200 -50 50 H V L CNN
F2 "" 200 100 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
C 65 0 111 0 1 10 N
C 100 -70 11 0 1 0 F
C 100 70 11 0 1 0 F
P 2 0 1 0 30 -70 100 -70 N
P 2 0 1 10 30 -50 30 -90 N
P 2 0 1 0 30 0 100 0 N
P 2 0 1 10 30 20 30 -20 N
P 2 0 1 0 30 70 100 70 N
P 2 0 1 10 30 90 30 50 N
P 2 0 1 0 100 -70 100 -100 N
P 2 0 1 0 100 -70 100 0 N
P 2 0 1 0 100 100 100 70 N
P 3 0 1 10 10 75 10 -75 10 -75 N
P 4 0 1 0 40 0 80 15 80 -15 40 0 F
P 4 0 1 0 100 -70 130 -70 130 70 100 70 N
P 4 0 1 0 110 20 115 15 145 15 150 10 N
P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
X G 1 -200 0 210 R 50 50 1 1 I
X S 2 100 -200 100 U 50 50 1 1 P
X D 3 100 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# R
#
DEF R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "R" 0 0 50 V V C CNN
F2 "" -70 0 50 V V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
R_*
Resistor_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# R_Pack04
#
DEF R_Pack04 RN 0 0 Y N 1 F N
F0 "RN" -300 0 50 V V C CNN
F1 "R_Pack04" 200 0 50 V V C CNN
F2 "" 275 0 50 V I C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
DIP*
SOIC*
$ENDFPLIST
DRAW
S -250 -95 150 95 0 1 10 f
S -225 75 -175 -75 0 1 10 N
S -125 75 -75 -75 0 1 10 N
S -25 75 25 -75 0 1 10 N
S 75 75 125 -75 0 1 10 N
P 2 0 1 0 -200 -100 -200 -75 N
P 2 0 1 0 -200 75 -200 100 N
P 2 0 1 0 -100 -100 -100 -75 N
P 2 0 1 0 -100 75 -100 100 N
P 2 0 1 0 0 -100 0 -75 N
P 2 0 1 0 0 75 0 100 N
P 2 0 1 0 100 -100 100 -75 N
P 2 0 1 0 100 75 100 100 N
X R1.1 1 -200 -200 100 U 50 50 1 1 P
X R2.1 2 -100 -200 100 U 50 50 1 1 P
X R3.1 3 0 -200 100 U 50 50 1 1 P
X R4.1 4 100 -200 100 U 50 50 1 1 P
X R4.2 5 100 200 100 D 50 50 1 1 P
X R3.2 6 0 200 100 D 50 50 1 1 P
X R2.2 7 -100 200 100 D 50 50 1 1 P
X R1.2 8 -200 200 100 D 50 50 1 1 P
ENDDRAW
ENDDEF
#
# TFP401
#
DEF TFP401 U 0 40 Y Y 2 L N
F0 "U" 600 50 60 H V C CNN
F1 "TFP401" 200 50 60 H V C CNN
F2 "" 350 -1150 60 H I C CNN
F3 "" 350 -1150 60 H I C CNN
DRAW
S 700 0 0 -1700 1 1 0 f
S 1150 -4450 0 0 2 1 0 f
X PAD 101 350 -1900 200 U 50 50 1 1 W
X OVDD 18 900 -1050 200 L 50 50 1 1 W
X OGND 19 -200 -1050 200 R 50 50 1 1 W
X OGND 28 -200 -1150 200 R 50 50 1 1 W
X OVDD 29 900 -1150 200 L 50 50 1 1 W
X DVDD 38 900 -200 200 L 50 50 1 1 W
X DGND 39 -200 -200 200 R 50 50 1 1 W
X OVDD 43 900 -1250 200 L 50 50 1 1 W
X OGND 45 -200 -1250 200 R 50 50 1 1 W
X DGND 5 -200 -100 200 R 50 50 1 1 W
X OVDD 57 900 -1350 200 L 50 50 1 1 W
X OGND 58 -200 -1350 200 R 50 50 1 1 W
X DVDD 6 900 -100 200 L 50 50 1 1 W
X DVDD 67 900 -300 200 L 50 50 1 1 W
X DGND 68 -200 -300 200 R 50 50 1 1 W
X OGND 76 -200 -1450 200 R 50 50 1 1 W
X OVDD 78 900 -1450 200 L 50 50 1 1 W
X AGND 79 -200 -500 200 R 50 50 1 1 W
X AVDD 82 900 -500 200 L 50 50 1 1 W
X AGND 83 -200 -600 200 R 50 50 1 1 W
X AVDD 84 900 -600 200 L 50 50 1 1 W
X AGND 87 -200 -700 200 R 50 50 1 1 W
X AVDD 88 900 -700 200 L 50 50 1 1 W
X AGND 89 -200 -800 200 R 50 50 1 1 W
X AGND 92 -200 -900 200 R 50 50 1 1 W
X AVDD 95 900 -800 200 L 50 50 1 1 W
X PVDD 97 900 -1600 200 L 50 50 1 1 W
X PGND 98 -200 -1600 200 R 50 50 1 1 W
X DFO 1 -200 -1700 200 R 50 50 2 1 I
X QE0 10 -200 -2050 200 R 50 50 2 1 O
X OCK_INV 100 -200 -650 200 R 50 50 2 1 I
X QE1 11 -200 -2150 200 R 50 50 2 1 O
X QE2 12 -200 -2250 200 R 50 50 2 1 O
X QE3 13 -200 -2350 200 R 50 50 2 1 O
X QE4 14 -200 -2450 200 R 50 50 2 1 O
X QE5 15 -200 -2550 200 R 50 50 2 1 O
X QE6 16 -200 -2650 200 R 50 50 2 1 O
X QE7 17 -200 -2750 200 R 50 50 2 1 O
X ~PD 2 -200 -1300 200 R 50 50 2 1 I I
X QE8 20 -200 -2850 200 R 50 50 2 1 O
X QE9 21 -200 -2950 200 R 50 50 2 1 O
X QE10 22 -200 -3050 200 R 50 50 2 1 O
X QE11 23 -200 -3150 200 R 50 50 2 1 O
X QE12 24 -200 -3250 200 R 50 50 2 1 O
X QE13 25 -200 -3350 200 R 50 50 2 1 O
X QE14 26 -200 -3450 200 R 50 50 2 1 O
X QE15 27 -200 -3550 200 R 50 50 2 1 O
X ST 3 -200 -1000 200 R 50 50 2 1 I
X QE16 30 -200 -3650 200 R 50 50 2 1 O
X QE17 31 -200 -3750 200 R 50 50 2 1 O
X QE18 32 -200 -3850 200 R 50 50 2 1 O
X QE19 33 -200 -3950 200 R 50 50 2 1 O
X QE20 34 -200 -4050 200 R 50 50 2 1 O
X QE21 35 -200 -4150 200 R 50 50 2 1 O
X QE22 36 -200 -4250 200 R 50 50 2 1 O
X QE23 37 -200 -4350 200 R 50 50 2 1 O
X PIXS 4 -200 -1500 200 R 50 50 2 1 I
X CTL1 40 -200 -100 200 R 50 50 2 1 O
X CTL2 41 -200 -200 200 R 50 50 2 1 O
X CTL3 42 -200 -300 200 R 50 50 2 1 O
X ODCK 44 -200 -550 200 R 50 50 2 1 O C
X DE 46 -200 -450 200 R 50 50 2 1 O
X VSYNC 47 -200 -850 200 R 50 50 2 1 O
X HSYNC 48 -200 -750 200 R 50 50 2 1 O
X QO0 49 1350 -2050 200 L 50 50 2 1 O
X QO1 50 1350 -2150 200 L 50 50 2 1 O
X QO2 51 1350 -2250 200 L 50 50 2 1 O
X QO3 52 1350 -2350 200 L 50 50 2 1 O
X QO4 53 1350 -2450 200 L 50 50 2 1 O
X QO5 54 1350 -2550 200 L 50 50 2 1 O
X QO6 55 1350 -2650 200 L 50 50 2 1 O
X QO7 56 1350 -2750 200 L 50 50 2 1 O
X QO8 59 1350 -2850 200 L 50 50 2 1 O
X QO9 60 1350 -2950 200 L 50 50 2 1 O
X QO10 61 1350 -3050 200 L 50 50 2 1 O
X QO11 62 1350 -3150 200 L 50 50 2 1 O
X QO12 63 1350 -3250 200 L 50 50 2 1 O
X QO13 64 1350 -3350 200 L 50 50 2 1 O
X QO14 65 1350 -3450 200 L 50 50 2 1 O
X QO15 66 1350 -3550 200 L 50 50 2 1 O
X QO16 69 1350 -3650 200 L 50 50 2 1 O
X ~STAG 7 -200 -1200 200 R 50 50 2 1 I I
X QO17 70 1350 -3750 200 L 50 50 2 1 O
X QO18 71 1350 -3850 200 L 50 50 2 1 O
X QO19 72 1350 -3950 200 L 50 50 2 1 O
X QO20 73 1350 -4050 200 L 50 50 2 1 O
X QO21 74 1350 -4150 200 L 50 50 2 1 O
X QO22 75 1350 -4250 200 L 50 50 2 1 O
X QO23 77 1350 -4350 200 L 50 50 2 1 O
X SCDT 8 -200 -1100 200 R 50 50 2 1 O
X Rx2+ 80 1350 -850 200 L 50 50 2 1 O
X Rx2- 81 1350 -950 200 L 50 50 2 1 O
X Rx1+ 85 1350 -600 200 L 50 50 2 1 O
X Rx1- 86 1350 -700 200 L 50 50 2 1 O
X ~PDO 9 -200 -1400 200 R 50 50 2 1 I I
X Rx0+ 90 1350 -350 200 L 50 50 2 1 O
X Rx0- 91 1350 -450 200 L 50 50 2 1 O
X RxC+ 93 1350 -100 200 L 50 50 2 1 O
X RxC- 94 1350 -200 200 L 50 50 2 1 O
X EXT_RES 96 -200 -1800 200 R 50 50 2 1 I
X RSVD 99 -200 -1600 200 R 50 50 2 1 I
ENDDRAW
ENDDEF
#
# TFP410
#
DEF TFP410 U 0 40 Y Y 2 L N
F0 "U" 550 50 60 H V C CNN
F1 "TFP410" 150 50 60 H V C CNN
F2 "" -450 450 60 H I C CNN
F3 "" -450 450 60 H I C CNN
DRAW
S 0 0 850 -4250 1 1 0 f
S 0 0 700 -1000 2 1 0 f
X ~PD 10 -200 -4050 200 R 50 50 1 1 I I
X MSEN/PO1 11 -200 -3450 200 R 50 50 1 1 O
X ISEL/~RST 13 -200 -3550 200 R 50 50 1 1 I
X DSEL/SDA 14 -200 -3750 200 R 50 50 1 1 B
X BSEL/SCL 15 -200 -3650 200 R 50 50 1 1 I
X TFADJ 19 1050 -100 200 L 50 50 1 1 I X
X DE 2 -200 -2750 200 R 50 50 1 1 I
X TXC- 21 1050 -1150 200 L 50 50 1 1 O
X TXC+ 22 1050 -1050 200 L 50 50 1 1 O
X TX0- 24 1050 -400 200 L 50 50 1 1 O
X TX0+ 25 1050 -300 200 L 50 50 1 1 O
X TX1- 27 1050 -650 200 L 50 50 1 1 O
X TX1+ 28 1050 -550 200 L 50 50 1 1 O
X TX2- 30 1050 -900 200 L 50 50 1 1 O
X TX2+ 31 1050 -800 200 L 50 50 1 1 O
X RESERVED/GND 34 -200 -4150 200 R 50 50 1 1 U
X DKEN 35 -200 -3950 200 R 50 50 1 1 I
X DATA23 36 -200 -2400 200 R 50 50 1 1 I
X DATA22 37 -200 -2300 200 R 50 50 1 1 I
X DATA21 38 -200 -2200 200 R 50 50 1 1 I
X DATA20 39 -200 -2100 200 R 50 50 1 1 I
X HSYNC 4 -200 -2850 200 R 50 50 1 1 I
X DATA19 40 -200 -2000 200 R 50 50 1 1 I
X DATA18 41 -200 -1900 200 R 50 50 1 1 I
X DATA17 42 -200 -1800 200 R 50 50 1 1 I
X DATA16 43 -200 -1700 200 R 50 50 1 1 I
X DATA15 44 -200 -1600 200 R 50 50 1 1 I
X DATA14 45 -200 -1500 200 R 50 50 1 1 I
X DATA13 46 -200 -1400 200 R 50 50 1 1 I
X DATA12 47 -200 -1300 200 R 50 50 1 1 I
X VSYNC 5 -200 -2950 200 R 50 50 1 1 I
X DATA11 50 -200 -1200 200 R 50 50 1 1 I
X DATA10 51 -200 -1100 200 R 50 50 1 1 I
X DATA9 52 -200 -1000 200 R 50 50 1 1 I
X DATA8 53 -200 -900 200 R 50 50 1 1 I
X DATA7 54 -200 -800 200 R 50 50 1 1 I
X DATA6 55 -200 -700 200 R 50 50 1 1 I
X IDCK- 56 -200 -2550 200 R 50 50 1 1 I C
X IDCK+ 57 -200 -2650 200 R 50 50 1 1 I C
X DATA5 58 -200 -600 200 R 50 50 1 1 I
X DATA4 59 -200 -500 200 R 50 50 1 1 I
X CTL3 6 -200 -3050 200 R 50 50 1 1 I
X DATA3 60 -200 -400 200 R 50 50 1 1 I
X DATA2 61 -200 -300 200 R 50 50 1 1 I
X DATA1 62 -200 -200 200 R 50 50 1 1 I
X DATA0 63 -200 -100 200 R 50 50 1 1 I
X CTL2 7 -200 -3150 200 R 50 50 1 1 I
X CTL1 8 -200 -3250 200 R 50 50 1 1 I
X EDGE/HTPLG 9 -200 -3850 200 R 50 50 1 1 I
X DVDD 1 900 -100 200 L 50 50 2 1 W
X DVDD 12 900 -200 200 L 50 50 2 1 W
X DGND 16 -200 -100 200 R 50 50 2 1 W
X PGND 17 -200 -450 200 R 50 50 2 1 W
X PVDD 18 900 -450 200 L 50 50 2 1 W
X TGND 20 -200 -600 200 R 50 50 2 1 W
X TVDD 23 900 -600 200 L 50 50 2 1 W
X TGND 26 -200 -700 200 R 50 50 2 1 W
X TVDD 29 900 -700 200 L 50 50 2 1 W
X VREF 3 900 -800 200 L 50 50 2 1 W
X TGND 32 -200 -800 200 R 50 50 2 1 W
X DVDD 33 900 -300 200 L 50 50 2 1 W
X DGND 48 -200 -200 200 R 50 50 2 1 W
X NC 49 900 -900 200 L 50 50 2 1 N X
X DGND 64 -200 -300 200 R 50 50 2 1 W
X PAD 65 350 -1200 200 U 50 50 2 1 W
ENDDRAW
ENDDEF
#
#End Library

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2445
dvi-sniffer.net Normal file

File diff suppressed because it is too large Load Diff

View File

@@ -1,4 +1,4 @@
update=Sun 27 Nov 2016 03:27:06 PM CET
update=Sun 30 Sep 2018 10:38:43 PM CEST
version=1
last_client=kicad
[pcbnew]
@@ -27,41 +27,4 @@ NetIExt=net
version=1
[eeschema]
version=1
LibDir=../shimattapcblibs/schematics/ti;../shimattapcblibs/schematics/altera;../shimattapcblibs/schematics/power;../shimattapcblibs/schematics/passives
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=microcontrollers
LibName13=dsp
LibName14=microchip
LibName15=analog_switches
LibName16=motorola
LibName17=texas
LibName18=intel
LibName19=audio
LibName20=interface
LibName21=digital-audio
LibName22=philips
LibName23=display
LibName24=cypress
LibName25=siliconi
LibName26=opto
LibName27=atmel
LibName28=contrib
LibName29=valves
LibName30=ti
LibName31=altera
LibName32=regulators
LibName33=pmic
LibName34=powersym
LibName35=osc
LibName36=con-molex
LibDir=

View File

@@ -1,40 +1,4 @@
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:ti
LIBS:altera
LIBS:regulators
LIBS:pmic
LIBS:powersym
LIBS:osc
LIBS:con-molex
EESchema Schematic File Version 4
LIBS:dvi-sniffer-cache
EELAYER 26 0
EELAYER END
@@ -58,18 +22,18 @@ F1 "power.sch" 60
F2 "VIN" I L 1850 1550 60
$EndSheet
$Comp
L BARREL_JACK CON?
L dvi-sniffer-rescue:BARREL_JACK CON101
U 1 1 583A22E7
P 1050 1650
F 0 "CON?" H 1031 1975 50 0000 C CNN
F 1 "BARREL_JACK" H 1031 1884 50 0000 C CNN
F 2 "" H 1050 1650 50 0000 C CNN
F 0 "CON101" H 1031 1975 50 0000 C CNN
F 1 "PJ-002A" H 1031 1884 50 0000 C CNN
F 2 "Connectors:BARREL_JACK" H 1050 1650 50 0001 C CNN
F 3 "" H 1050 1650 50 0000 C CNN
1 1050 1650
1 0 0 -1
$EndComp
$Comp
L GND #PWR01
L dvi-sniffer-rescue:GND #PWR01
U 1 1 583A2391
P 1450 1850
F 0 "#PWR01" H 1450 1600 50 0001 C CNN
@@ -124,13 +88,14 @@ F9 "OCLK" O R 4950 1300 60
F10 "HSYNC" O R 4950 1400 60
F11 "VSYNC" O R 4950 1500 60
F12 "PDOWN" I R 4950 2750 60
F13 "CEC" B R 4950 3100 60
$EndSheet
Text Label 5300 1100 0 60 ~ 0
DATI[0..23]
Wire Wire Line
1350 1650 1450 1650
Wire Wire Line
1450 1650 1450 1850
1450 1650 1450 1750
Wire Wire Line
1450 1750 1350 1750
Connection ~ 1450 1750
@@ -176,6 +141,7 @@ F11 "HOTPLUG" O L 9700 1950 60
F12 "DKEN" I L 9700 2350 60
F13 "EDGE" I L 9700 2450 60
F14 "PDOWN" I L 9700 2750 60
F15 "CEC" B L 9700 3050 60
$EndSheet
Wire Wire Line
8100 1300 9700 1300
@@ -200,9 +166,9 @@ Wire Wire Line
Wire Wire Line
8100 1700 9700 1700
Wire Wire Line
9700 2350 8150 2350
8100 2350 9700 2350
Wire Wire Line
9700 2450 8150 2450
8100 2450 9700 2450
Wire Wire Line
4950 2750 5950 2750
Wire Wire Line
@@ -212,6 +178,115 @@ Wire Wire Line
Wire Wire Line
8300 3350 8300 2750
Wire Wire Line
8100 2750 9700 2750
8100 2750 8300 2750
Connection ~ 8300 2750
Wire Bus Line
8100 3100 8800 3100
Entry Wire Line
8800 4900 8900 5000
Entry Wire Line
8800 4800 8900 4900
Entry Wire Line
8800 4700 8900 4800
Entry Wire Line
8800 4600 8900 4700
Entry Wire Line
8800 4500 8900 4600
Entry Wire Line
8800 4400 8900 4500
Entry Wire Line
8800 4300 8900 4400
Entry Wire Line
8800 4200 8900 4300
Wire Wire Line
8900 4300 9250 4300
Wire Wire Line
8900 4400 9250 4400
Wire Wire Line
8900 4500 9250 4500
Wire Wire Line
8900 4600 9250 4600
Wire Wire Line
9250 4700 8900 4700
Wire Wire Line
8900 4800 9250 4800
Wire Wire Line
9250 4900 8900 4900
Wire Wire Line
8900 5000 9250 5000
Text Label 8350 3100 0 60 ~ 0
GPIO[0..7]
Text Label 8900 4300 0 60 ~ 0
GPIO0
Text Label 8900 4400 0 60 ~ 0
GPIO1
Text Label 8900 4500 0 60 ~ 0
GPIO2
Text Label 8900 4600 0 60 ~ 0
GPIO3
Text Label 8900 4700 0 60 ~ 0
GPIO4
Text Label 8900 4800 0 60 ~ 0
GPIO5
Text Label 8900 4900 0 60 ~ 0
GPIO6
Text Label 8900 5000 0 60 ~ 0
GPIO7
Wire Wire Line
8900 4200 8900 3800
$Comp
L dvi-sniffer-rescue:GND #PWR02
U 1 1 584D1EA7
P 8900 3800
F 0 "#PWR02" H 8900 3550 50 0001 C CNN
F 1 "GND" H 8905 3627 50 0000 C CNN
F 2 "" H 8900 3800 50 0000 C CNN
F 3 "" H 8900 3800 50 0000 C CNN
1 8900 3800
-1 0 0 1
$EndComp
$Comp
L dvi-sniffer-rescue:+3V3 #PWR03
U 1 1 584D223B
P 9100 3800
F 0 "#PWR03" H 9100 3650 50 0001 C CNN
F 1 "+3V3" H 9100 3950 50 0000 C CNN
F 2 "" H 9100 3800 50 0000 C CNN
F 3 "" H 9100 3800 50 0000 C CNN
1 9100 3800
1 0 0 -1
$EndComp
Wire Wire Line
9100 3800 9100 4100
Wire Wire Line
9100 4100 9250 4100
$Comp
L dvi-sniffer-rescue:CONN_01X10 P101
U 1 1 587A3F51
P 9450 4550
F 0 "P101" H 9528 4591 50 0000 L CNN
F 1 "CONN_01X10" H 9528 4500 50 0000 L CNN
F 2 "Pin_Headers:Pin_Header_Angled_1x10_Pitch2.54mm" H 9450 4550 50 0001 C CNN
F 3 "" H 9450 4550 50 0000 C CNN
1 9450 4550
1 0 0 -1
$EndComp
Wire Wire Line
8900 4200 9250 4200
Wire Wire Line
4950 3100 5400 3100
Wire Wire Line
5400 3100 5400 3450
Wire Wire Line
5400 3450 9450 3450
Wire Wire Line
9450 3450 9450 3050
Wire Wire Line
9450 3050 9700 3050
Wire Wire Line
1450 1750 1450 1850
Wire Wire Line
8300 2750 9700 2750
Wire Bus Line
8800 3100 8800 4900
$EndSCHEMATC

2488
dvi-sniffer.xml Normal file

File diff suppressed because it is too large Load Diff

66
dvi.pretty/dvi.kicad_mod Normal file
View File

@@ -0,0 +1,66 @@
(module dvi (layer F.Cu)
(descr "DVI connector, Tyco P/N 1-1734147-1")
(fp_text reference DVI (at 0 6.10108) (layer F.SilkS)
(effects (font (thickness 0.3048)))
)
(fp_text value JP*** (at 0 -10.795) (layer F.SilkS)
(effects (font (thickness 0.3048)))
)
(fp_line (start -12.573 -9.017) (end -14.097 -7.493) (layer F.SilkS) (width 0.381))
(fp_line (start -14.097 -7.493) (end -14.097 -3.302) (layer F.SilkS) (width 0.381))
(fp_line (start 14.224 -7.62) (end 14.224 -3.302) (layer F.SilkS) (width 0.381))
(fp_line (start 12.573 -9.017) (end 14.224 -7.62) (layer F.SilkS) (width 0.381))
(fp_line (start -12.573 -9.017) (end -12.573 -0.508) (layer F.SilkS) (width 0.381))
(fp_line (start 12.573 -9.017) (end 12.573 -0.508) (layer F.SilkS) (width 0.381))
(fp_line (start -18.415 -0.508) (end -18.415 -3.302) (layer F.SilkS) (width 0.381))
(fp_line (start -18.415 -3.302) (end -12.573 -3.302) (layer F.SilkS) (width 0.381))
(fp_line (start 18.415 -0.508) (end 18.415 -3.302) (layer F.SilkS) (width 0.381))
(fp_line (start 18.415 -3.302) (end 12.573 -3.302) (layer F.SilkS) (width 0.381))
(fp_line (start 18.415 -0.508) (end 18.415 2.54) (layer F.SilkS) (width 0.381))
(fp_line (start -18.415 -0.508) (end -18.415 2.54) (layer F.SilkS) (width 0.381))
(fp_line (start -18.415 -0.508) (end 18.415 -0.508) (layer F.SilkS) (width 0.381))
(fp_line (start -12.573 -9.017) (end 12.573 -9.017) (layer F.SilkS) (width 0.381))
(fp_line (start -12.065 9.017) (end 12.065 9.017) (layer F.SilkS) (width 0.381))
(fp_line (start 12.065 9.017) (end 12.065 2.54) (layer F.SilkS) (width 0.381))
(fp_line (start -12.065 9.017) (end -12.065 2.54) (layer F.SilkS) (width 0.381))
(fp_line (start -18.415 2.54) (end 18.415 2.54) (layer F.SilkS) (width 0.381))
(pad "" thru_hole circle (at 15.11046 -3.302) (size 3.50012 3.50012) (drill 1.89992) (layers *.Cu *.Mask))
(pad 3 thru_hole circle (at -5.715 -7.112) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 2 thru_hole circle (at -7.62 -7.112) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 1 thru_hole circle (at -9.525 -7.112) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 4 thru_hole circle (at -3.81 -7.112) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 5 thru_hole circle (at -1.905 -7.112) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 9 thru_hole circle (at -9.525 -5.207) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 7 thru_hole circle (at 1.905 -7.112) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 6 thru_hole circle (at 0 -7.112) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad "" thru_hole circle (at -15.11046 -3.302) (size 3.50012 3.50012) (drill 1.89992) (layers *.Cu *.Mask))
(pad 10 thru_hole circle (at -7.62 -5.207) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 11 thru_hole circle (at -5.715 -5.207) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 12 thru_hole circle (at -3.81 -5.207) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 13 thru_hole circle (at -1.905 -5.207) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 14 thru_hole circle (at 0 -5.207) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 15 thru_hole circle (at 1.905 -5.207) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 16 thru_hole circle (at 3.81 -5.207) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 17 thru_hole circle (at -9.525 -3.302) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 18 thru_hole circle (at -7.62 -3.302) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 19 thru_hole circle (at -5.715 -3.302) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 20 thru_hole circle (at -3.81 -3.302) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 21 thru_hole circle (at -1.905 -3.302) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 22 thru_hole circle (at 0 -3.302) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 23 thru_hole circle (at 1.905 -3.302) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 24 thru_hole circle (at 3.81 -3.302) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad 8 thru_hole circle (at 3.81 -7.112) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad C2 thru_hole circle (at 9.525 -6.477) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad C1 thru_hole circle (at 6.985 -6.477) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad C3 thru_hole circle (at 6.985 -3.937) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad C4 thru_hole circle (at 9.525 -3.937) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad C5 thru_hole circle (at 8.255 -7.747) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad C5 thru_hole circle (at 8.255 -2.667) (size 1.30048 1.30048) (drill 0.8001) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -9.525 -0.00254) (size 1.99898 1.99898) (drill 1.99898) (layers *.Cu))
(pad "" np_thru_hole circle (at 9.525 -0.00254) (size 1.99898 1.99898) (drill 1.99898) (layers *.Cu))
(model walter/conn_pc/dvi.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)

1654
dvi_in.sch

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

5
fp-lib-table Normal file
View File

@@ -0,0 +1,5 @@
(fp_lib_table
(lib (name smd)(type KiCad)(uri "$(SHIMATTADIR)/footprints/pretty/smd.pretty")(options "")(descr ""))
(lib (name dvi)(type KiCad)(uri "$(KIPRJMOD)/dvi.pretty")(options "")(descr ""))
(lib (name artwork)(type KiCad)(uri "$(SHIMATTADIR)/footprints/pretty/artwork.pretty")(options "")(descr ""))
)

1272
fpga.sch

File diff suppressed because it is too large Load Diff

1197
power.sch

File diff suppressed because it is too large Load Diff

3
sym-lib-table Normal file
View File

@@ -0,0 +1,3 @@
(sym_lib_table
(lib (name dvi-sniffer-rescue)(type Legacy)(uri ${KIPRJMOD}/dvi-sniffer-rescue.lib)(options "")(descr ""))
)